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Contributor
Contributor
376 Views
Registered: ‎08-29-2016

Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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I am using the Logicore MIPI v4.1 Dphy Rx product in the Virtex UltraScale Plus, and it is successfully interfacing to another FPGA (this other FPGA is acting as the MIPI Tx) via the FMC connector. 

Is it possible to access the Low Power Lanes directly, from that MIPI IP ? There are a number of flags in the IP that signal the beginning of transmission, end of transmission etc but none that offer direct access to the Low Power lanes for data and clock. 

Please let me know how to directly access these signals for the Dphy Rx IP

 

(edited to clarify which is RX and which is Tx)

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Xilinx Employee
Xilinx Employee
303 Views
Registered: ‎03-30-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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Hello @gmoore 

You are on your own if you want to modify MIPI D-PHY IP.
Xilinx do not support customized IP. Please understand that.

IS_MANAGED.png

Vivado reset your IP generated RTL, because the IP has IS_MANAGED parameter set true.
Please try to use the following command to prevent Vivado reset the output RTL, before doing any RTL editting.
set_property IS_LOCKED true [get_files mipi_dphy_0.xci]

Regards
Leo

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5 Replies
Xilinx Employee
Xilinx Employee
361 Views
Registered: ‎03-30-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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Hello @gmoore 

Pardon me but I cannot understand your post.
You are using MIPI v4.1 D-PHY RX IP as  MIPI Tx ?? That's not possible.

Can you share a picture to explain your question ?


Thanks
Leo

Contributor
Contributor
354 Views
Registered: ‎08-29-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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Apologies - the v4.1 IP is acting as a MIPI Rx. It is receiving MIPI Data from another FPGA. This other FPGA is the MIPI Tx. My sentence may have been poorly phrased 

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Contributor
Contributor
341 Views
Registered: ‎08-29-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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Hi,

 

I have found a solution - there are low power signals located within the MIPI DPHY Rx Core. I attempted to edit the .v files within the DPhy Rx to bring these out to top level (editing my_name_support.v,my_name_c1.v, my_name_core.v and my_name.v ). I was able to change the read/write permissions on these files to edit them. 

However, when I run the Synthesis step, it fails, as if the edits made to the .v files are not active. Is there a process flow for making manual edits to these .v files in an IP, and running the Synthesis step ? I do not want the IP to be re-generated each time, as this will re-generate the .v files and remove my edits each time. 

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Xilinx Employee
Xilinx Employee
304 Views
Registered: ‎03-30-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

Jump to solution

Hello @gmoore 

You are on your own if you want to modify MIPI D-PHY IP.
Xilinx do not support customized IP. Please understand that.

IS_MANAGED.png

Vivado reset your IP generated RTL, because the IP has IS_MANAGED parameter set true.
Please try to use the following command to prevent Vivado reset the output RTL, before doing any RTL editting.
set_property IS_LOCKED true [get_files mipi_dphy_0.xci]

Regards
Leo

View solution in original post

Contributor
Contributor
294 Views
Registered: ‎08-29-2016

Re: Access to Low Power Lanes in MIPI D-PHY v4.1 Rx IP

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Thanks karnanl - that solved my issue with Synthesis, and the modified Phy successfully passed synthesis.