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Registered: ‎10-25-2012

Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

I wonder is anybody sucessfully make the Triple Frame Buffer Example works (in simulation) with VDMA 6.0? To be note, it must be VDMA 6.0 instead of old version VDMA (I made VDMA 5.04 works but 6.0 does not).

 

Triple Frame Buffer Example is very basic and I did same configuration as PG020, but I confronted weird problem  that 'tready" of  AXIs s2mm goes low and never assert after 3 frames. I checked possible errors like AXI ID width mismatch, register configuration. But I did not find any problems.

 

If anybody has experience make the VDMA 6.0 works, I hope we can discuss here to see whether there is anyother potential reason to casue AXIs s2mm path stuck in VDMA.

 

Thanks in advance.

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Anyone can help? Thanks.
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Registered: ‎05-31-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi, i worked with version 5, i remember that in the example given for the triple buffer, 1 bit was set incorrectly.

The DMA was programmed for transferring only 1 frame. It's the frame count bit in the s2mm control register.

Maybe in the VDMA 6 they have copied the example. Check your control register bits..

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Thanks very much, mrbietola.

I did make the VDMA 5.04 working. I figured out there is mistake in their old example as you mentioned.

However, in this VDMA 6.0, I pay attention to the potential problems I confronted in VDMA 5.04. I read out status register (0x04 and 0x34), they are all 0x0000_0000, which means there is no error in VDMA. But 'tready" of AXIs s2mm goes low and never assert, that is very weird I can't understand what is going on.

So I wonder is anybody has direct experience in VDMA 6.0

Thanks again.
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Registered: ‎05-31-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi, i have an other hint.

I had a similar behavior with the scaler. It has always low the ready signal. So i did a custom reset logic to reset the scaler for at least 20 cycle at the start.

Then it worked!

It seems to me that some logic must be initialized by a long reset, you could try with that.

Or maybe is the option Flush on frame synch deasserted? If you have deasserted it , in case of erroneous configuration of the DMA, the interface might stop working

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Thanks very much, mrbietola. I will try your hint soon.

For your scaler, you mentioned "It has always low the ready signal", does it be low since beginning or it deasserts after several frames? In my case, the VDMA works well at the first three frames then "tready" becomes "0" and never come back.

What do you mean "maybe is the option Flush on frame synch deasserted?"

Thanks so much for your hints. I sincerely appreciate it.

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Registered: ‎05-31-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

don't remember if always low.

If you flush on fsync, even if your dma have a wrong configuration, it continues to work .

If flush on fsync is disabled, and your dma has a wrong configuration, it stops.

I'm not 100% sure about this, check in the documentation. Check also the "ready" keyword in the documentation.

 

 

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi mrbietola, I try to use a long reset but the problem still exists. I still try to investigate the reason.

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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hello,

 

Yes, for me it's working well in a video custom application.

I use VIVADO 2013.1 and the design grab a video coming from a TVP5150 (PAL 50Hz 720x576 interlaced) and output it to a TFT LVDS panel (60Hz 1024x768 non interlaced)

 

=> VDMA 6.0 with 3 buffer.

 

 

Best regards,

Christian

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Thanks to post here, Christian.

So in your design:
1. Do you use AXI interconnect to connect VDMA with DDR3?
2. Which genlock mode you use in VDMA s2mm and mm2s?

Thanks very much.
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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi,

 

I use

axi_interconnect version 1.06.a

mig_7series 1.9.a (DDR3 KC705 board)

axi_vdma 6.0

 

Genclock config

 

vdma.jpg

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

That is pretty interesting. Your design is very similar as mine. Do you mind upload the HDL file which you instance VDMA, Interconnect, MIG DDR3 controller and connect them?

Thanks very much.
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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi,

 

Herewith you can find the structure....

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Thanks so much, let me have a look on that.

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi christian, I checked your file. It seems all your module is drive by ui_clock from DDR3 controller. So both AXI interconnect and AXI VDMA are working in sync mode (no need to work in async), right?

During your development, have you confront any problems like the system is working at the beginning but then pause forever?

I checked my design simulation, it looks like that DDR3 controller stops sending "bvalid" to AXI interconnect after severl frames. I don't know what reason can cause this, have you ever confront similar problems?

Thanks very much.
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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi,

 

Yes you are right I made all domain crossing at the input/output of my design beacause of FIFO use.... Thus, all the middle of the design is stricltly in SYNC mode. During the design, I tried ASYNC mode in VDMA and AXI interconnectect but in VIVADO 2014.4.1 (old IP core) and it also worked.

 

I reread your first post and maybe I'm wrong... I never tried any complete simulation of my design more than 1 or 2 pictures.....

I made a lot of simulation and try (in real) with small bricks.

 

Thus, my design is functining perfectly in real with KC705 board and with custom board (with other DDR3 configuration --> 32 bits instead of 64 bits)

 

My design is relatively simple ... I have a input frequency of max 27MHz, a working frequency of 100MHz (all AXI bus), a DDR frequency of 200MHz and 400MHz (4:1), and a output of 65 MHz/455MHz for the LVDS.

 

Did you tried your design in real ???

 

Kind regards,

Christian

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Registered: ‎05-31-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi christian, i'm using the VDMA controlled by microblaze.

I see that you use a master axi lite to control it right?

This axi_lite_master_vdma is a custom component?

Where did you start to develop it?

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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hello,

 

Yes I use a master axi lite to control it.

axi_lite_master_vdma is not a custom design but I customized it for my application of course.

 

If you google "axi_lite_master", you will find some link

for example

https://github.com/ShepardSiegel/hotline/tree/master/doc/axi_examples

 

Christian

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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

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Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

I am using AXI4-Lite master to do VDMA configuration too. I did try my design in VC707, but it does not work.

In my simulation, I make the frame size very small to 60*40, therefore I can easily simulate 10 frames with short duration.

I am still investigating whether there is something wrong between AXI interconnect and DDR3 controller, it is pretty weird.

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi Christian,

It seems I found the porblem, I did not connect AXI4 ID (e.g. BID) of AXI interconnect slave side (which connect with VDMA) to ground. Although VDMA does not use AXI ID, but AXI interconnect needs these ID be fixed. After connected them with ground, my design works in simulation.

But I confronted another problem after I do implementation of my design. My design does not meet timing requirements and when I run the design on board, it does not work although the design works in behavioral simulation.

I know your design is sync design since you only use one clock (ui_clk). Did you confront timing issue when you do implementation of your design?

You mentioned you also try async design, have you confront any timing issue when you make you design async?

Thanks very much.
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Registered: ‎03-22-2013

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi,

 

AXI4 ID

 

s01_axi_bid and s00_axi_bid are output for axi interconnect ... how do you connect them to ground ? And I don't have any BID signal on the VDMA!

 

If I remember well, I had also some timing issue but my design worked even if the frequency crossing was made by the VDMA (async mode).

 

After changing my design from "async" -->  "sync" (crossing VDMA --> crossing at input/output) I solved the timing issue.

 

For my point of view, the timing issue are juste bad timing constraint (set_max_delay -datapath_only) present or not in the IP core.

 

Best regards,

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Registered: ‎10-25-2012

Re: Anybody make the Triple Frame Buffer Example works (in simulation) sucessfully described in PG020 with VDMA 6.0?

Hi Christian,

The "arid" and "awid" of AXI interconnect in slave sides need to connect with ground.

It seems the timing issue comes from the DDR3 controller, I will investigate more to see what happened.

Thanks so much for your help.
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