05-26-2013 09:30 AM
I wonder is anybody sucessfully make the Triple Frame Buffer Example works (in simulation) with VDMA 6.0? To be note, it must be VDMA 6.0 instead of old version VDMA (I made VDMA 5.04 works but 6.0 does not).
Triple Frame Buffer Example is very basic and I did same configuration as PG020, but I confronted weird problem that 'tready" of AXIs s2mm goes low and never assert after 3 frames. I checked possible errors like AXI ID width mismatch, register configuration. But I did not find any problems.
If anybody has experience make the VDMA 6.0 works, I hope we can discuss here to see whether there is anyother potential reason to casue AXIs s2mm path stuck in VDMA.
Thanks in advance.
05-28-2013 02:03 AM
Hi, i worked with version 5, i remember that in the example given for the triple buffer, 1 bit was set incorrectly.
The DMA was programmed for transferring only 1 frame. It's the frame count bit in the s2mm control register.
Maybe in the VDMA 6 they have copied the example. Check your control register bits..
05-28-2013 07:03 AM
05-28-2013 11:33 PM
Hi, i have an other hint.
I had a similar behavior with the scaler. It has always low the ready signal. So i did a custom reset logic to reset the scaler for at least 20 cycle at the start.
Then it worked!
It seems to me that some logic must be initialized by a long reset, you could try with that.
Or maybe is the option Flush on frame synch deasserted? If you have deasserted it , in case of erroneous configuration of the DMA, the interface might stop working
05-29-2013 06:34 AM
05-30-2013 12:46 AM
don't remember if always low.
If you flush on fsync, even if your dma have a wrong configuration, it continues to work .
If flush on fsync is disabled, and your dma has a wrong configuration, it stops.
I'm not 100% sure about this, check in the documentation. Check also the "ready" keyword in the documentation.
06-01-2013 07:14 PM
06-13-2013 06:50 AM
Yes, for me it's working well in a video custom application.
I use VIVADO 2013.1 and the design grab a video coming from a TVP5150 (PAL 50Hz 720x576 interlaced) and output it to a TFT LVDS panel (60Hz 1024x768 non interlaced)
=> VDMA 6.0 with 3 buffer.
06-13-2013 06:56 AM
06-13-2013 07:05 AM
axi_interconnect version 1.06.a
mig_7series 1.9.a (DDR3 KC705 board)
06-13-2013 07:24 AM
06-13-2013 07:40 AM
06-13-2013 07:41 AM
06-13-2013 05:25 PM
06-13-2013 10:30 PM
Yes you are right I made all domain crossing at the input/output of my design beacause of FIFO use.... Thus, all the middle of the design is stricltly in SYNC mode. During the design, I tried ASYNC mode in VDMA and AXI interconnectect but in VIVADO 2014.4.1 (old IP core) and it also worked.
I reread your first post and maybe I'm wrong... I never tried any complete simulation of my design more than 1 or 2 pictures.....
I made a lot of simulation and try (in real) with small bricks.
Thus, my design is functining perfectly in real with KC705 board and with custom board (with other DDR3 configuration --> 32 bits instead of 64 bits)
My design is relatively simple ... I have a input frequency of max 27MHz, a working frequency of 100MHz (all AXI bus), a DDR frequency of 200MHz and 400MHz (4:1), and a output of 65 MHz/455MHz for the LVDS.
Did you tried your design in real ???
06-13-2013 11:30 PM
Hi christian, i'm using the VDMA controlled by microblaze.
I see that you use a master axi lite to control it right?
This axi_lite_master_vdma is a custom component?
Where did you start to develop it?
06-13-2013 11:59 PM
Yes I use a master axi lite to control it.
axi_lite_master_vdma is not a custom design but I customized it for my application of course.
If you google "axi_lite_master", you will find some link
06-14-2013 12:02 AM
06-14-2013 07:11 AM
06-16-2013 12:24 PM
06-17-2013 12:26 AM
s01_axi_bid and s00_axi_bid are output for axi interconnect ... how do you connect them to ground ? And I don't have any BID signal on the VDMA!
If I remember well, I had also some timing issue but my design worked even if the frequency crossing was made by the VDMA (async mode).
After changing my design from "async" --> "sync" (crossing VDMA --> crossing at input/output) I solved the timing issue.
For my point of view, the timing issue are juste bad timing constraint (set_max_delay -datapath_only) present or not in the IP core.
06-17-2013 06:42 PM