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Visitor abhijitd1973
Visitor
270 Views
Registered: ‎03-27-2019

Basic TPG design is not working

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Hi,

I have created basic TPG design for Arty S7-50, using Vivado 2019.1 but unable to get display. There are no critical warnings and bitstream generation is successful. Can someone please help me identify possible issues with this so that I can fix it?

Below are more details:

  1. input clock - sys_clock @ 12 Mhz, Output clocks - CLK1-100Mhz, CLK-2-25 Mhz, Reset is Active Low
  2. Timing controller does not have detection enabled.Video mode 640x480p, VSYNC and HSYNC have LOW, others HIGH.
  3. TPG has default settings. Samples per clock- 1, max data width - 8, max columns 4096, max rows 2160.
  4. AXI2Video- native video output component width - 8, clock mode - independant,Timing mode - master
  5. RGB2VGA configured for RGB each having depth of 4.
  6. Display is through Digilent PMODVGA connected to JB and JC.
  7. Design, constraint file is attached for your review.
  8. synthesis option - global / out of context, tried both. No critical warnings for either of these.

thank you so much for your time, pl let me know if any additional info is to be furnished.

best regards,

Abhijit

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1 Solution

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Scholar watari
Scholar
245 Views
Registered: ‎06-16-2013

Re: Basic TPG design is not working

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Hi @abhijitd1973 

 

Would you make sure these floating ports ?

 

- clken on v_tc_0

- aclken on v_axi4s_vid_out_0

- vid_io_out_reset on v_axi4s_vid_out_0

 

Also, would you make sure the following signals by ILA, too ?

 

- locked on v_axi4s_vid_out_0

- overflow on v_axi4s_vid_out_0

- underflow on v_axi4s_vid_out_0

- status on v_axi4s_vid_out_0

 

And, would you refer or/and read Xilinx video seriases, too ?

 

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-6-From-AXI4-Stream-to-Native-Video/td-p/862633

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-7-How-does-the-AXI4-Stream-to-Video-Out-IP/td-p/864467

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-8-Debugging-the-AXI4-Stream-to-Video-Out/td-p/866346

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-16-Understanding-Video-Timing-with-the-VTC/td-p/899769

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-31-Debugging-a-Video-System-using-an-ILA/ba-p/1004299

 

Best regards,

 

4 Replies
Scholar watari
Scholar
246 Views
Registered: ‎06-16-2013

Re: Basic TPG design is not working

Jump to solution

Hi @abhijitd1973 

 

Would you make sure these floating ports ?

 

- clken on v_tc_0

- aclken on v_axi4s_vid_out_0

- vid_io_out_reset on v_axi4s_vid_out_0

 

Also, would you make sure the following signals by ILA, too ?

 

- locked on v_axi4s_vid_out_0

- overflow on v_axi4s_vid_out_0

- underflow on v_axi4s_vid_out_0

- status on v_axi4s_vid_out_0

 

And, would you refer or/and read Xilinx video seriases, too ?

 

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-6-From-AXI4-Stream-to-Native-Video/td-p/862633

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-7-How-does-the-AXI4-Stream-to-Video-Out-IP/td-p/864467

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-8-Debugging-the-AXI4-Stream-to-Video-Out/td-p/866346

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-16-Understanding-Video-Timing-with-the-VTC/td-p/899769

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-31-Debugging-a-Video-System-using-an-ILA/ba-p/1004299

 

Best regards,

 

Moderator
Moderator
193 Views
Registered: ‎11-21-2018

Re: Basic TPG design is not working

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Hi @abhijitd1973 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).
 
If this is not solved/answered, please reply in the topic giving more information on your current status.
 
Thanks and Regards,

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor abhijitd1973
Visitor
181 Views
Registered: ‎03-27-2019

Re: Basic TPG design is not working

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Hi @watari 

Thank you so much for sharing the useful links. I have reviewed those and it appears to me that TPG, VTC and AXI4Stream2VideoOut all need to be clocked to the same frequency - pl. correct me if I am wrong in my understanding. I have made corresponding change to clk=40MhZ now (800x600p). I am getting 'did not meet timing requirements', underflow is high. To avoid domain crossing logic, I have configured common clock for AXI4Stream2VideoOut. I have attached the ILA and modified design for your review please. 

As suggested in the AXI4Stream2VideoOut debug note, I plan to test it using higher clock frequencies (720p) and/or introduce VDMA/FB before AXI4Stream2VideoOut to see if it helps, will post my findings.

Thank you once again for looking into this, request your suggestion so that I can fix this.

best regards,

Abhijit

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Scholar watari
Scholar
162 Views
Registered: ‎06-16-2013

Re: Basic TPG design is not working

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Hi @abhijitd1973 

 

Here are my suggestion.

 

1) Connect a wire between clk_wiz0/locked and proc_sys_reset_0/dmc_locked to inhibit unexpected behaviour.

2) Consider FIFO size to avoid overflow and/or underflow, even if you use same clock between video processing path.

 

Note)

At least, I strongly recommend to modify 1), even if you already succeed it.

 

Best regards,