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Visitor
Visitor
7,813 Views
Registered: ‎04-11-2011

Bit Reversal Question on FFT Core

Is the FFT Core (7.1) capable of accepting bit-reversed inputs and outputing the data in natural order?  Specifically, I have a signal that I want to process using a forward FFT core configured to output the result in bit-reversed order.  I then want to take the resulting data into an inverse FFT core, also configured to output the data in bit-reversed order, resulting in its output data being in natural order.  I am able to successfully simulate with both cores configured for natural order inputs/outputs, but to save on resoursces/latency, I would like to configure the forward and inverse FFT cores to use bit-reversed outputs.

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Visitor
Visitor
7,769 Views
Registered: ‎04-11-2011

Re: Bit Reversal Question on FFT Core

Any insight on this question would be much appreciated, even if the answer is no.  I'm led to believe the FFT core is not compatible with bit-reversed inputs, but would like confirmation from those more experienced in the matter since I am relatively new to using this core.

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Visitor
Visitor
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Registered: ‎08-31-2011

Re: Bit Reversal Question on FFT Core

Actually I'm interested in this topic too.

 

An option for bit-reversed inputs would be especially useful for doing fast convolution using overlap-discard and overlap-add methods. Since this is basically a FFT followed by an IFFT, it would be very resource efficient if both cores could work with bit-reversed outputs and inputs respectively.

 

Unfortunately this is not possible since the FFT/IFFT cores support  only bit reversed outputs, and I don't see an easy way of getting a bit-reversed input IFFT from a bit-reversed output IFFT. 

 

I wonder how am I supposed to implement fast convolution using coregen-FFTs. The only options I can think of is using the BRAM-expensive natural order FFT and IFFT.

 

 

 

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Xilinx Employee
Xilinx Employee
7,682 Views
Registered: ‎08-02-2011

Re: Bit Reversal Question on FFT Core

bpelger is correct, Bit reverse input is not supported at this time.

 

Natural order FFT/IFFT will allow implementation of fast convolution algorithms.

www.xilinx.com
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Visitor
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7,678 Views
Registered: ‎08-31-2011

Re: Bit Reversal Question on FFT Core

I just had the impression that fast convolution is such a standard task, that I must be missing an option or something else in coregen. Thanks for the clarification. 

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Xilinx Employee
Xilinx Employee
7,674 Views
Registered: ‎11-28-2007

Re: Bit Reversal Question on FFT Core

Could you please open a webcase requesting FFT core supporting inputs in bit-reversed order? If yes, please send me the webcase number via PM.

 


@bpelger wrote:

I just had the impression that fast convolution is such a standard task, that I must be missing an option or something else in coregen. Thanks for the clarification. 




Cheers,
Jim
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Newbie
Newbie
7,568 Views
Registered: ‎10-11-2010

Re: Bit Reversal Question on FFT Core

Did anyone open up a ticket for this as mentioned in the last response by Jimwu?
I am very interested in FFT core with bit reversal output and input back into IFFT (with the same bit reversal order) and get natural order out.

Thanks
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Xilinx Employee
Xilinx Employee
7,566 Views
Registered: ‎08-02-2011

Re: Bit Reversal Question on FFT Core

Yes, a case was opened for this. The possibility for bit reversed input is being investigated. No firm plans at this point, though.

 

I recommend you contact your FAE and provide feedback to them so they can communicate with marketing.

www.xilinx.com
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Newbie
Newbie
6,834 Views
Registered: ‎06-23-2013

Re: Bit Reversal Question on FFT Core

Am I missing something?

 

A basic 10-bit counter gives an output A9..A0 [A0 is lsb].  Add that to a register and you get a source pointer.

By flipping the order of the output pins PURELY IN CODE [A0..A9], and adding to a second register, you get a target pointer.

Incrementing the counter would automatically sort the destination data into bit-reversed order [or vice versa].

 

With source data untouched, you can have multiple ovelapping FFTs being solved in parallel. Throw in a DSP48 slice and a lookup table, and you can apply a window to the data as you transfer it, before the FFT starts.

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