09-11-2019 07:57 AM
I've a problem with the interrupt of the "Buffer frame video write", if I use a 4k 30Hz video (hdmi rx subsystem) the system works fine (the interrupt of the "Buffer frame video write" is generated every 33.3ms), if I put a 4k 60Hz the system fails. In particular the interrupt of the "Buffer frame video write" is generated every 1.5s and not every 16.6ms, I checked the Tuser and it's correct (16.6ms).
The design is done in this way: Hdmi rx -> an AXI4-Stream Switch -> FIFO -> buffer frame video write -> vcu
09-11-2019 08:49 AM
09-11-2019 02:04 PM
It seems bandwidth issue.
Would you make sure the followings ?
- Consider and make sure clock frequency in your video path
- Consider and make sure bus width in your video path
- Make sure QoS setting of VCU, if necessary.
I recommend to share block diagram and your clock tree, if you want more suggestion.
09-12-2019 01:13 AM - edited 09-12-2019 01:13 AM
For 4k 60 the hdmi bus is setted to 4 pixels per clock; the "Buffer frame video write" for 4 pixels uses a bus of 256bit, but the zynq (S_AXI_HP0_FPD) can manage a maximum of 128bit so I need to "convert" 4 pixel to 2 pixel per clock, for this purprose I used a clock converter from 148.5MHz (used by 4 pixels per clock) to 330MHz (for 2 pixels per clock) and than I put an "AXI4-Stream Data Width Converter" to get 2 pixel per clock at 330MHz (In this way I can manage 1080p 60 and 4k 30). I have the same problem also when I use the "Buffer frame video write" to write the frames into the memory without the vcu working.
09-12-2019 01:28 AM
09-12-2019 01:41 AM
As you mentioned before, it's bandwidth issue.
Would you change the following ?
Plan a) Change FIFO size to 8192x64bit.
Plan b) Change clock frequency to over 356.4[MHz].
Plan c) Consider bus witdh and so on.
09-12-2019 02:06 AM
I'm using the xilinx board zcu106, so I can't go over 333MHz, the zynq bus width it's fixed to 128bits and I've already tried the FIFO with 8192 but it does not solve the problem.
09-12-2019 04:04 AM
Its a zynq ultra scale plus part,
That can do over 350 MHz internal clock.
The Zynq bus width fixed at 128 bits ? thats interesting.
Are you feeding the video through the processor ?
( sorry I can't see the orriginal posts on the phone )
Is this 333 MHz your processor speed / external memory speed ?
what speed is the PL side clock ?
09-12-2019 04:08 AM
Ive just checked,
have you tried the TRD for this board ?
This says it can work at 4K 60Hz
Its always easier and quicker to modify a working design,
I'd suggets you take that desing and prove the system as is works,
then take bits out / add to it as you want.
09-12-2019 05:46 AM
The 333 MHz it's the limit of the ps bus (S_AXI_HP0_FPD), I can set 360MHz but I get this critical warning (" [BD 17-146] Maximum Supported frequency for zynq_ultra_ps/saxihp0_fpd_aclk is 333.333"). The zynq ps bus can be set to a maximum 128bit, the "Buffer frame video write" needs 128bits for 2 pixels per clock.
09-12-2019 05:54 AM
Is it the PS speed that you think is causing the problem ?
What have you set the PL clock to ?
Is it the PS width that you think is causing the problem ?
What have you se tthe PL AXI bus bandwidth for ?
have you tried the TRD ?
09-12-2019 06:25 AM
In the PL I have two clocks: one (148.5MHz) for the hdmi 4 pixels per clock than I use a 333MHz when I convert from 4 pixels to 2 (I'm going at the maximum speed "allowed"). Maybe the problem is the "Buffer frame video write" that uses 128 bits for only two pixels (YUV422) when with 128 bits you can put more pixels (YUV422). If the ps bus had 256 bits then I could stay with the current clock and set the "Buffer frame video write" to 4 pixels per clock, if instead it supported a higher clock I could leave the bus width unchanged and go faster. I've started from the TRD.
09-12-2019 08:51 AM
Let us know how yo uget on with the TRD,
It says that can run at 4K60Hz, so should be a good pointer as to what you can do.
09-12-2019 02:39 PM
Would you make sure the following ?
- What frequency do you use DRAM in Zynq ?
- Did you set QoS parameter ?
=> I'm not familiar with it. But I guess the following URL might help for you.
09-12-2019 11:51 PM
I've found that adding a queue in gstreamer solve the problem and now the interrupt of "Buffer video write" it's correct.