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Adventurer
Adventurer
518 Views
Registered: ‎01-19-2018

CSI 2 Tx PacketFooter

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Hello,

1. The CSI 2 Tx PAcketizes with Word count f00 but the receiver reads the Word count f40 ... (Data type YUV_422 8bit and 1920x1080p 60 Hz resolution) its actually 1920 x 2 bytes for 1 HS packet
2. Do we have the control over packet footer setting in CSI 2 TX IP? in Rx we seen Cyclic REdundancy Check (CRC)Error
3. Rx has Start Of Transmission (SOT)error for 2 lanes among the 4 lanes configuration..

Regards,
Prassanna Daram

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Adventurer
Adventurer
428 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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@karnanl

>So your system connectivity looks like above.
same as above
If you can ensure that Xilinx MIPI CSI-2 TX IP register reported :
- Controller Ready is asserted. ( Address offset 0x00 ) Yes asserted to logic '1'
- Line buffer full is not asserted. ( Address offset 0x24 )
- Pixel Data Under-run is not asserted. ( Address offset 0x24 )
then thisis not the problem of MIPI TX. ( Please kindly confirm this )
"
CSI-2 TX Status:
-------------
Core Enable:                1
Soft Reset:                   0
Controller Ready:         1
ULPS Entry:                 0
Non-continuous clock: 0

Protocol Configuration Register: 0x201B
Generic Short packet Register: 0x0000
Line COunt Virtual Channel 0: 0x0000

Interrupt Status Register: 0x0000 (0x24)

"
>Since the Jetson TX2 reported CRC error and SoT error, the error root cause could be on the connectivity HW itself.
"Rx receives WordCount Data ID VC and all these".,,, the computed CRC in Rx is not same as the PAcketized CRC from PacketFooter

>Do you have a good quality MIPI signals on Jetson TX2 input pins ? Have you check the signal waveform using oscilloscope ?
Oscilloscope data wont tell CRC errors right?
Kind regards
Leo

-- BTW, do you use MIPI CSI-2 TX Subsystem from the latest Vivado (2018.1 or 2018.2) ??
 MIPI CSI-2 TX Subsystem 2.0 2018.2

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Xilinx Employee
Xilinx Employee
490 Views
Registered: ‎03-30-2016

Re: CSI 2 Tx PacketFooter

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Hello Prassanna Daram @daram123

>1. The CSI 2 Tx PAcketizes with Word count f00 but the receiver reads the Word count f40 ... (Data type YUV_422 8bit and 1920x1080p 60 Hz resolution) its actually 1920 x 2 bytes for 1 HS packet

Is it simulation or HW result ?
Could you please check the TX IP register ? Do you have buffer-full or pixel under-run flag asserted ?

>2. Do we have the control over packet footer setting in CSI 2 TX IP? in Rx we seen Cyclic REdundancy Check (CRC)Error

As mentioned by MIPI CSI-2 spec, Packet footer is only for CRC data.
User can choose to enable/disable CRC logic during IP generation, but no other modification allowed.

>3. Rx has Start Of Transmission (SOT)error for 2 lanes among the 4 lanes configuration..

Okay, CRC error and SOT error are not good.
 

Could you please kindly share your system block diagram ??
What is the MIPI TX device ? What is RX device ? ( US+ ? 7-series? Image-sensor ?)
If one or both of them are Xilinx devices could you please share the XCI file ?
How do you connect TX and RX ? Is there any external devices you are using ?
Did you set the same line number for both TX & RX ?

Kind regards,
Leo

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Adventurer
Adventurer
482 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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Hello @karnanl

It is a real-time Hardware result.

Packet footer is only for CRC data.
user can choose to enable/disable CRC logic during IP generation, but no other modification allowed.


Could you please kindly share your system block diagram ??
Enclosed.
What is the MIPI TX device ? What is RX device ? ( US+ ? 7-series? Image-sensor ?)
TX - Inrevium FMCL and 7 series FPGA Rx - Jetson TX2 NVIDIA
If one or both of them are Xilinx devices could you please share the XCI file ?
How do you connect TX and RX ? Is there any external devices you are using ?
Custom adapter board design by our company
Did you set the same line number for both TX & RX ?
Yes of course. They are given same line number

Regards,
Prasanna Daram

PocketStream_FPGA.png
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Xilinx Employee
Xilinx Employee
473 Views
Registered: ‎03-30-2016

Re: CSI 2 Tx PacketFooter

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Hello Prassanna Daram @daram123

XF_KC705_vs_Jetson_TX2_s.png
So your system connectivity looks like above.

If you can ensure that Xilinx MIPI CSI-2 TX IP register reported :
- Controller Ready is asserted. ( Address offset 0x00 )
- Line buffer full is not asserted. ( Address offset 0x24 )
- Pixel Data Under-run is not asserted. ( Address offset 0x24 )
then thisis not the problem of MIPI TX. ( Please kindly confirm this )

Since the Jetson TX2 reported CRC error and SoT error, the error root cause could be on the connectivity HW itself. Do you have a good quality MIPI signals on Jetson TX2 input pins ? Have you check the signal waveform using oscilloscope ?

Kind regards
Leo

-- BTW, do you use MIPI CSI-2 TX Subsystem from the latest Vivado (2018.1 or 2018.2) ??

Adventurer
Adventurer
360 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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@karnanl

>So your system connectivity looks like above.
Yes. Same as above.
>If you can ensure that Xilinx MIPI CSI-2 TX IP register reported :
- Controller Ready is asserted. ( Address offset 0x00 ) Asserted
- Line buffer full is not asserted. ( Address offset 0x24 )
- Pixel Data Under-run is not asserted. ( Address offset 0x24 ) - Not asserted
then this is not the problem of MIPI TX. ( Please kindly confirm this )
Prints were
"
CSI-2 TX Status:
-------------
Core Enable:                1
Soft Reset:                   0
Controller Ready:         1
ULPS Entry:                 0
Non-continuous clock: 0

Protocol Configuration Register: 0x201B
Generic Short packet Register: 0x0000
Line COunt Virtual Channel 0: 0x0000

Interrupt Status Register: 0x0000 (0x24)
"
Not the problem of Tx.....

>Since the Jetson TX2 reported CRC error and SoT error, the error root cause could be on the connectivity HW itself.
It was able to read DAtaatype VC and Word COunt from the packet.

>Do you have a good quality MIPI signals on Jetson TX2 input pins ? Have you check the signal waveform using oscilloscope ?

Kind regards
Leo

-- BTW, do you use MIPI CSI-2 TX Subsystem from the latest Vivado (2018.1 or 2018.2) ??
MIPI CSI-2 TX Subsystem 2.0 2018.2


Regards,
Prasanna Daram

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Adventurer
Adventurer
429 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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@karnanl

>So your system connectivity looks like above.
same as above
If you can ensure that Xilinx MIPI CSI-2 TX IP register reported :
- Controller Ready is asserted. ( Address offset 0x00 ) Yes asserted to logic '1'
- Line buffer full is not asserted. ( Address offset 0x24 )
- Pixel Data Under-run is not asserted. ( Address offset 0x24 )
then thisis not the problem of MIPI TX. ( Please kindly confirm this )
"
CSI-2 TX Status:
-------------
Core Enable:                1
Soft Reset:                   0
Controller Ready:         1
ULPS Entry:                 0
Non-continuous clock: 0

Protocol Configuration Register: 0x201B
Generic Short packet Register: 0x0000
Line COunt Virtual Channel 0: 0x0000

Interrupt Status Register: 0x0000 (0x24)

"
>Since the Jetson TX2 reported CRC error and SoT error, the error root cause could be on the connectivity HW itself.
"Rx receives WordCount Data ID VC and all these".,,, the computed CRC in Rx is not same as the PAcketized CRC from PacketFooter

>Do you have a good quality MIPI signals on Jetson TX2 input pins ? Have you check the signal waveform using oscilloscope ?
Oscilloscope data wont tell CRC errors right?
Kind regards
Leo

-- BTW, do you use MIPI CSI-2 TX Subsystem from the latest Vivado (2018.1 or 2018.2) ??
 MIPI CSI-2 TX Subsystem 2.0 2018.2

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Adventurer
Adventurer
400 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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All good! setup is working!!!

Adventurer
Adventurer
340 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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@@karnanl


CSI-2 TX Status:
-------------
Core Enable:                1
Soft Reset:                   0
Controller Ready:         1
ULPS Entry:                 0
Non-continuous clock: 0

Protocol Configuration Register: 0x201B
Generic Short packet Register: 0x0000
Line COunt Virtual Channel 0: 0x0000

Interrupt Status Register: 0x0001


CSI-2 D-PHY Status:
-------------
D-PHY Control Register: 0x0002
Initialization Timer: 0xF4240
HS_TIMEOUT: 0x10005
ESC_TIMEOUT: 0x6400
Clock Lane Status: 0x0009
Data Lane0 Status: 0xCEB0048
Data Lane1 Status: 0xCEB0048
Data Lane2 Status: 0xCEB0048
Data Lane3 Status: 0xCEB0048

Data Lane0 Status: 0xCEB0048
Data Lane1 Status: 0xCEB0048
Data Lane2 Status: 0xCEB0048
Data Lane3 Status: 0xCEB0009

data lane is being in Low-Power mode for long time and very rarely transits to High-Speed mode.. this happens in PassThrough. differently, Color Pattern no such issues.

""Receiver reads multiple word counts esp. different for every packet."" in pass it through mode


regards,
Prasanna Daram

 

 

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Adventurer
Adventurer
260 Views
Registered: ‎01-19-2018

Re: CSI 2 Tx PacketFooter

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@karnanlcSi2 Tx ..setting the buffer depth to16384 and 1024.. what is the relation between the input video resolution and the buffer size.?

Regards,
PRasanna Daram

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Xilinx Employee
Xilinx Employee
250 Views
Registered: ‎03-30-2016

Re: CSI 2 Tx PacketFooter

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Hello Prasanna Daram

Could you please create a new thread for different topic.
It help us and moderator tracking un-answered question.

Answer:
As recommended by PG260 Chapter4 "Configuration Tab", please set internal buffer depth, at least 2-3 lines of image data.

Thanks & regards
Leo
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