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1,013 Views
Registered: ‎08-08-2017

CSI-2 tx core quad pixel per beat problem

Hi,

 

We are currently using the YUV422 video format to transmit 16 bits data in a non vidéo application. The core work fine in single pixel per beat, hovewer if we feed the core in quad pixel per beat (pg260 p14) the data are scrambled.

Do anyone have experienced a similar issue with the CSI-2 tx core ?

 

Thanks

 

 

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Moderator
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1,010 Views
Registered: ‎11-09-2015

Re: CSI-2 tx core quad pixel per beat problem

Hi eric.dube@leddartech.com,

 

Please make sure the following condition is met on your design:

Where s_axis_aclk*Pixel_width*Pixel_Mode is approximately equal to 2 or 3 times of (TxByteClk*No_Lanes*8).

 

MIPI.PNG

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-08-2017

Re: CSI-2 tx core quad pixel per beat problem

Hi Florent,

How do I determine the speed of the TxByteClk signal ?

We have used 4 lanes at 1 Gbps in pixel mode 4 with a s_axis_aclk of 160 Mhz for a input bandwidth of (16*4*160) that more that twice the output bandwidth of 4 Gbps.

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Registered: ‎11-09-2015

Re: CSI-2 tx core quad pixel per beat problem

Hi eric.dube@leddartech.com,

 

Txbyteclk is line_rate/8.0. So indeed your input seems ok.

 

Then could you check the HW debug section from the PG:

debug.PNG

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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