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Observer
Observer
4,561 Views
Registered: ‎12-07-2008

Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hi All,

 

I have design in Simulink developed using system generator. In order to verify my design I need to input some signals from external source to FPGA. I want to perform Hardware in the Loop (HIL) simulation to obtain FPGA response in simulink. I want to lock GatewayIn with FPGA pin so that I can input signals from external source. I searched for it but do not found any solution for it. Can any one tell me how I can connect Gate-way_In and Gateway_out simulink signals to FPGA physical pins? 

 

Thank you very much,

Regards,

Umer.

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Xilinx Employee
Xilinx Employee
4,547 Views
Registered: ‎08-02-2011

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

SysGen User Guide. 'Using Hardware Co-Simulation' chapter. 'Board-Specific I/O Ports' section

www.xilinx.com
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Observer
Observer
4,536 Views
Registered: ‎12-07-2008

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hi Thanks for the reply.

 

But I am facing another problem. I generate a Hardware Cosim block for a simple design. But when I run the design I come across with this error:

 

Error creating a session.
Error occurred during "Simulation Initialization".

 

Below I have attached the pic of my design along with error.

 

System Gen error.png

 

Please advice me why this error is coming up?

 

I am using ISE 14.5 64-bit with MATLAB 2012b 64-bit.

 

Thanks,

Umer

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Contributor
Contributor
4,497 Views
Registered: ‎10-31-2010

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hello Umer,

 

See this blog post by my friend Jay Manvar "Hardware Inline Co-Simulation with output on FPGA development board"  http://bit.ly/11U0XZg

 

See the discussion topic "Can we get output on FPGA board using HW Co-Simulation?" http://forums.xilinx.com/t5/DSP-Tools/Can-we-get-output-on-FPGA-board-using-HW-Co-Simulation/td-p/234464

 

I hope these 2 links will help you in getting your output.

 

Regards

Vihang Naik
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Observer
Observer
4,491 Views
Registered: ‎12-07-2008

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hi Vihang,

 

I am extremely thankful for your so needed reply. Currently I am facing another problem that I explained in my last message. I am unable to access my SP605 board from simulink. I am using windows 7 with Xilinx ISE 14.5 and MATLAB 2012b. When I generate co-simulation block in simulink model, it give me error that it is unable to create a session for hardware cosimulation. I try to dig out the problem but still unable to solve it. Apparently MATLAB 2012b is working for system generator but it seems to me that it is unable to perform hardware cosimulation.

 

Can you please give me any suggestion on this issue?

Again thank you very much for your help.

 

Kind Regards,

M.Umer Farooq

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Contributor
Contributor
4,473 Views
Registered: ‎10-31-2010

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hello Umer,

 

See the similar post on "Error creating a session. Error occurred during "Simulation Initialization", Sysgen13.3, Matlab2011a"

http://forums.xilinx.com/t5/DSP-Tools/Error-creating-a-session-Error-occurred-during-quot-Simulation/td-p/226939

 

Regards,

 

Vihang Naik
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Observer
Observer
4,459 Views
Registered: ‎12-07-2008

Re: Connecting GatewayIn and Gatewayout blocks to physical FPGA pins for Hardware in the loop simulation

Hi Vihang,

 

Thank you very much for the post. It really works and my board is working now.

 

Best Regards,

Umer

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