06-17-2013 08:38 AM
I have some problems with the usage of the complex multiplier generated by the CoreGen. I am using Xilinx 14.1 and Verilog and I am using Xilinx only for both design & simulation. Right now I am just instantiating a complex multiplier and trying to verify if my understanding is correct. However, I have some questions:
* What is the meaning of s_axis_a_tvalid / s_axis_b_tvalid? I was thinking that they show if the inputs are valid. However, I set them to 0 and still the output value changes.
* Can I apply a new input every clock cycle and receive their (new inputs) results after n clock cycles where n is the latency? Or do I have to wait the output of a multiplication to feed the new values?
Thank you very much for your help.
06-18-2013 07:46 AM
s_axis_*_tvalid inded are used by a master IP to indicate that tdata bus contains valid data. Can you post a screenshot of the sim where tying them to 0 still results in changing output data? Also, can you post your .xco file?
As long as tready is asserted, the core will accept new data. The amount of latency depends on your configuration of the core. The core may have differing amounts of pipelining.
06-22-2013 09:04 PM
Sorry for such a late response. I am attaching a waveform to show the behavior. In the waveform, I am showing the signals of the complex multiplier I have instantiated. Even though the input valid bits are set to 0, the output changes when the inputs change. Also, for the aclk input of the complex multiplier, I am using my clk (which is supposed to run ~400MHz); is that fine?