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Adventurer
Adventurer
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Registered: ‎08-01-2018

Could I configure 5 MP resolution for VPSS IP cores ?

I would like to know if I can use 2592x1944 resolution for a videostream when using VPSS modules?

In SDK 2017.3 I see that the resolution is not supported by the driver

 

Thanks,

     Mihaita

 

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7 Replies
Moderator
Moderator
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Registered: ‎10-04-2017

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hi @mivascu85,

 

The VPSS core supports resolutions up to UHD at 60FPS for the V2.0 core and higher resolutions for the V2.1 core. (See PG231)

If you want to use custom resolutions, you will need to add these to your application. I know that most of our connectivity example designs show how to do this (DP/HDMI). I would recommend looking at the HDMI menu to see how this is done and if you have any questions to post to the forum.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Registered: ‎11-09-2015

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hi @mivascu85 

Is everything clear for you on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
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Registered: ‎08-01-2018

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hello,

 

   Sorry for the late reply I was out of office. And thanks for your reply.

   I have tried adding new resolution in XVidC_VideoMode enum (xvidc.h for video_common 4.4. driver) and XVidC_VideoTimingModes enum (xvideo_timings_table.c for video_common 4.4. driver) but I get some artefacts in the images I fetch from so I assume one chance is that configuration is not enough?

 

    i am using 2018.2 SDK

 

Thanks,

      Mihaita

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hi @mivascu85,

 

Can you post an image so we know what your artifacts look like? 

If you can post what the expected (no-artifact) image is as well, sometimes this is also helpful.

 

Thanks,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Adventurer
Adventurer
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Registered: ‎08-01-2018

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hello,

 

    Thanks for your reply. I have posted 2 images with problesm one for 25922x1944 and the one for 640x480.

    It can be seen that two image is duplicated somehow horizontally and there is some artefact on the right side.

    The images are fetched from a VDMA,. The VPSS writes the content in VDMA.

    the 2592x1944 resolution was not supported by the video_common_4 xilinx driver but I have added in config:

  in xvidc.h

XVIDC_VM_2560x1600_120_P_RB,
XVIDC_VM_2592x1944_60_P,
XVIDC_VM_3840x2160_24_P,

 

and in xvidc_timings_table.c

 

{ XVIDC_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVIDC_FR_120HZ,
{2560, 48, 32, 80, 2720, 1,
1600, 3, 6, 85, 1694, 0, 0, 0, 0, 0} },
{ XVIDC_VM_2592x1944_60_P, "2592x1944@60Hz", XVIDC_FR_60HZ,
{2592, 192, 280, 472, 3504, 0,
1944, 3, 6, 49, 2000, 0, 0, 0, 0, 1} },
{ XVIDC_VM_3840x2160_24_P, "3840x2160@24Hz", XVIDC_FR_24HZ,
{3840, 1276, 88, 296, 5500, 1,
2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} },

 

  The VPSS config is the following. Debug mode does not report any issue. I can confirm that correct video mode is selected by the VPSS driver. when changing the resolution I make sure I reset the core using API.

   The idea is that we have two VPSS instances and do YUV422 -> YUV444 -> RGB conversion. I want to achieve just a colour conversion with VPSS nos caling.

   From YUV422 to RGB. For that we use 2 instances: one does YUV422 to YUV444 and the next one does YUV444 to RGB.

   On the VDMA side we have 3 bytes per pixel and configure the stride accordingly  but I do not set the stride on VPSS(don't know how). I assumed that if I have bits per colour = 8 will give me the expected stride(24 bits) as is on VDMA.

   I know the images look like there is a stride issue.

 

int VisualCameraInit::initializeVPSS()
{
/* Local variables */
XVidC_VideoMode resIdIn, resIdOut;
XVidC_VideoStream StreamIn1, StreamOut1;
XVidC_VideoStream StreamIn2, StreamOut2;
int widthIn, heightIn, widthOut, heightOut;
XVidC_VideoTiming const *TimingPtr;

int status = XST_FAILURE;

if (_resolution == 5)
{
widthIn = STILL_FULL_WIDTH;
heightIn = STILL_FULL_HEIGHT;

widthOut = STILL_FULL_WIDTH;
heightOut = STILL_FULL_HEIGHT;
}
else
{

widthIn = STILL_BIN_WIDTH;
heightIn = STILL_BIN_HEIGHT;

widthOut = STILL_BIN_WIDTH;
heightOut = STILL_BIN_HEIGHT;
}


XVprocSs *InstancePtr1 = (XVprocSs*)malloc(sizeof(XVprocSs));
XVprocSs *InstancePtr2= (XVprocSs*)malloc(sizeof(XVprocSs));

XVprocSs_Config *CfgPtr1 = XVprocSs_LookupConfig(XPAR_VCAM_STILLIMAGE_Y422TOY444_DEVICE_ID/*XPAR_VCAM_STILL_IMAGE_Y422TOY444_DEVICE_ID*/);

 

// if (CfgPtr1 != NULL)
XVprocSs_CfgInitialize(InstancePtr1, CfgPtr1, CfgPtr1->BaseAddress);


// XVprocSs_Stop(&InstancePtr1);

 

XVprocSs_Config *CfgPtr2 = XVprocSs_LookupConfig(XPAR_VCAM_STILLIMAGE_YUVTORGB_DEVICE_ID/*XPAR_VCAM_STILL_IMAGE_YUVTORGB_DEVICE_ID*/);
XVprocSs_CfgInitialize(InstancePtr2, CfgPtr2, CfgPtr2->BaseAddress);
//XVprocSs_Stop(&InstancePtr2);

resIdIn = XVidC_GetVideoModeId(widthIn, heightIn, XVIDC_FR_60HZ,
FALSE);

resIdOut = XVidC_GetVideoModeId(widthOut, heightOut, XVIDC_FR_60HZ,
FALSE);


//Get the resolution details

TimingPtr = XVidC_GetTimingInfo(resIdIn);

XVidC_SetVideoStream(&StreamIn1, resIdIn, XVIDC_CSF_YCRCB_422, XVIDC_BPC_8, XVIDC_PPC_1);
StreamIn1.VmId = resIdIn;
StreamIn1.Timing = *TimingPtr;
StreamIn1.Timing.HActive = widthIn;
StreamIn1.Timing.VActive = heightIn;
StreamIn1.ColorFormatId = XVIDC_CSF_YCRCB_422;
StreamIn1.ColorDepth = (XVidC_ColorDepth)InstancePtr1->Config.ColorDepth;
StreamIn1.PixPerClk = (XVidC_PixelsPerClock)InstancePtr1->Config.PixPerClock;
StreamIn1.FrameRate = XVIDC_FR_60HZ;
StreamIn1.IsInterlaced = 0;

 

status = XVprocSs_SetVidStreamIn(InstancePtr1, &StreamIn1);
if (status != XST_SUCCESS) {
xil_printf("Unable to set input video stream parameters correctly\r\n");
return XST_FAILURE;
}

XVidC_SetVideoStream(&StreamOut1, resIdOut, XVIDC_CSF_YCRCB_444, XVIDC_BPC_8, XVIDC_PPC_1);

StreamOut1.VmId = resIdIn;
StreamOut1.Timing = *TimingPtr;
StreamOut1.Timing.HActive = widthOut;
StreamOut1.Timing.VActive = heightOut;
StreamOut1.ColorFormatId = XVIDC_CSF_YCRCB_444;
StreamOut1.ColorDepth = /*XVIDC_BPC_8*/ (XVidC_ColorDepth)InstancePtr1->Config.ColorDepth;
StreamOut1.PixPerClk = /*XVIDC_PPC_2*/ (XVidC_PixelsPerClock)InstancePtr1->Config.PixPerClock;
StreamOut1.FrameRate = XVIDC_FR_60HZ;
StreamOut1.IsInterlaced = 0;

status = XVprocSs_SetVidStreamOut(InstancePtr1, &StreamOut1);
if (status != XST_SUCCESS) {
xil_printf("Unable to set output video stream parameters correctly\r\n");
return XST_FAILURE;
}

XVidC_SetVideoStream(&StreamIn2, resIdIn, XVIDC_CSF_YCRCB_444, XVIDC_BPC_8, XVIDC_PPC_1);
StreamIn2.VmId = resIdIn;
StreamIn2.Timing = *TimingPtr;
StreamIn2.Timing.HActive = widthOut;
StreamIn2.Timing.VActive = heightOut;
StreamIn2.ColorFormatId = XVIDC_CSF_YCRCB_444;
StreamIn2.ColorDepth = (XVidC_ColorDepth)InstancePtr2->Config.ColorDepth;
StreamIn2.PixPerClk = (XVidC_PixelsPerClock)InstancePtr2->Config.PixPerClock;
StreamIn2.FrameRate = XVIDC_FR_60HZ;
StreamIn2.IsInterlaced = 0;

status = XVprocSs_SetVidStreamIn(InstancePtr2, &StreamIn2);
if (status != XST_SUCCESS) {
xil_printf("Unable to set input video stream parameters correctly\r\n");
return XST_FAILURE;
}

XVidC_SetVideoStream(&StreamOut2, resIdOut, XVIDC_CSF_RGB, XVIDC_BPC_8, XVIDC_PPC_1);
StreamOut2.VmId = resIdOut;
StreamOut2.Timing = *TimingPtr;
StreamOut2.Timing.HActive = widthOut;
StreamOut2.Timing.VActive = heightOut;
StreamOut2.ColorFormatId = XVIDC_CSF_RGB/*XVIDC_CSF_RGB*/;
StreamOut2.ColorDepth = (XVidC_ColorDepth)InstancePtr2->Config.ColorDepth;
StreamOut2.PixPerClk = (XVidC_PixelsPerClock)InstancePtr2->Config.PixPerClock;
StreamOut2.FrameRate = XVIDC_FR_60HZ;
StreamOut2.IsInterlaced = 0;

status = XVprocSs_SetVidStreamOut(InstancePtr2, &StreamOut2);
if (status != XST_SUCCESS) {
xil_printf("Unable to set output video stream parameters correctly\r\n");
return XST_FAILURE;
}

status = XVprocSs_SetSubsystemConfig(InstancePtr1);
if (status != XST_SUCCESS) {
xil_printf("XVprocSs_SetSubsystemConfig failed %d\r\n", status);
return XST_FAILURE;
}

status = XVprocSs_SetSubsystemConfig(InstancePtr2);
if (status != XST_SUCCESS) {
xil_printf("XVprocSs_SetSubsystemConfig failed %d\r\n", status);
return XST_FAILURE;
}

XVprocSs_Start(InstancePtr1);
XVprocSs_Start(InstancePtr2);

#ifdef VPSS_DEBUG
//Query video processing subsystem configuration
XVprocSs_ReportSubsystemConfig(InstancePtr1);
XVprocSs_LogDisplay(InstancePtr1);

XVprocSs_ReportSubsystemConfig(InstancePtr2);
XVprocSs_LogDisplay(InstancePtr2);
#endif

return status;
}

 

Thanks,

       Mihaita

BadImage_5MP.PNG
BadImage_VGA.PNG
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Adventurer
Adventurer
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Registered: ‎08-01-2018

Re: Could I configure 5 MP resolution for VPSS IP cores ?

And here is some debug output:

 

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: YUV_422
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 2592x1944@60Hz
Pixel Clock: 420480000

->OUTPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 2592x1944@60Hz
Pixel Clock: 420480000

 


VPSS log
-----------
Info: Subsystem start init
Info: Topology is HCResample-only
Info: HCResampler coefficients loaded
Info: HCResampler init
Info: Subsystem reset
Info: Subsystem ready
Info: Subsystem configuration is valid
Info: HCResampler-only configuration is valid
Info: HCResampler start
Info: Subsystem start
<RTOS-C1> [77803][Important][VisualCameraControlTask] VisualCameraControlTask (IRQ-Handler): Error
log end
-----------

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 2592x1944@60Hz
Pixel Clock: 420480000

->OUTPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 2592x1944@60Hz
Pixel Clock: 420480000

 


VPSS log
-----------
Info: Subsystem start init
Info: Topology is Csc-only
Info: Csc init
Info: Subsystem reset
Info: Subsystem ready
Info: Subsystem configuration is valid
Info: Csc-only configuration is valid
Info: Csc start
Info: Subsystem start
log end

Stopped VPSS pipeline successfully!

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: YUV_422
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 640x480@60Hz
Pixel Clock: 25200000

->OUTPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 640x480@60Hz
Pixel Clock: 25200000

 


VPSS log
-----------
Info: Subsystem start init
Info: Topology is HCResample-only
Info: HCResampler coefficients loaded
Info: HCResampler init
Info: Subsystem reset
Info: Subsystem ready
Info: Subsystem configuration is valid
Info: HCResampler-only configuration is valid
Info: HCResampler start
Info: Subsystem start
log end
-----------

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 640x480@60Hz
Pixel Clock: 25200000

->OUTPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 640x480@60Hz
Pixel Clock: 25200000

 


VPSS log
-----------
Info: Subsystem start init
Info: Topology is Csc-only
Info: Csc init
Info: Subsystem reset
Info: Subsystem ready
Info: Subsystem configuration is valid
Info: Csc-only configuration is valid
Info: Csc start
Info: Subsystem start
log end

 

Thanks,

      Mihaita

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: Could I configure 5 MP resolution for VPSS IP cores ?

Hi @mivascu85,

 

This happens more than you would expect, can you confirm that your incoming resolution is actually 2592x1944?

What IP do you have before/after the VPSS? Can you put ILAs in your system to verify the line lengths before and after every IP? This will validate that the correct resolution is being pushed into the VPSS and will also tell us if the issue is directly with the VPSS or due to another IP.

 

Some of our IP requires that the horizontal timing is divisible by 2, but it looks like your timing is fine for this

{ XVIDC_VM_2592x1944_60_P, "2592x1944@60Hz", XVIDC_FR_60HZ,
{2592, 192, 280, 472, 3504, 0,
1944, 3, 6, 49, 2000, 0, 0, 0, 0, 1} },

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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