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Participant srdjan.opacic
Participant
346 Views
Registered: ‎08-21-2017

DP RX Subsystem FIFO overflow

Hi,

I'm running DP RX subsystem with 150 MHz output clock. Output from DP is native interface, vsync, hsync, etc... On a single DP source (optical link receiver, resolution 4k@60Hz) I get scrambled data on output (bad hsync vsync waveforms, not just bad pixels), and mostly Timing FIFO overflow (register 0x110 in DP receiver is 0x100=, but sometimes all 3 FIFOs are overflowing, (register 0x110 is 0x111). Is this a possible data stream misalignment, or overflow due to too slow clock? What is the recommended clock for DP output when working with 4k resolution?

Thanks

Srdjan

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17 Replies
Moderator
Moderator
343 Views
Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow

HI @srdjan.opacic ,

I believe a 150MHz clock should be enough for 4K60.

For 4K60, the pixel clock is ~555MHz. If you devide by 4 lanes you get ~140Mhz.

You can also MVID and NVID to generate the video clock. This is what should be done in the example design.

Just adding that the PG recommend to use a clock up to 200MHz if you have fifo issue:

displayport.JPG

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar watari
Scholar
331 Views
Registered: ‎06-16-2013

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic 

 

How do you generate pixel recovery clock with Mvid and Nvid for native video interface ?

If your architecture is generated pixel recovery clock independently, it occurs FIFO overflow or underflow.

 

Also, FIFO overflow is related to video timing.

What video timing do you use ? VESA reduced blanking ? or other ?

 

Best regards,

Participant srdjan.opacic
Participant
302 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

I'm using various timings on input (depending on use case), my idea was to use a fixed clock for output from DP. My understanding was that in that case I simply always get data_valid which is intermittent during one line - which is fine by me. Am I wrong?

The timing in question (which produces error) is a custom modification - but speaking generally, I would like to have a solution which can adapt to any timing.

Best regards

Srdjan

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Participant srdjan.opacic
Participant
301 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Update - MVid = 32359, NVid = 32768. We use line rate for clock reference in this calculation, right? In our case it is 5.4 Gbps.

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Moderator
Moderator
291 Views
Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow


@srdjan.opacic wrote:

I'm using various timings on input (depending on use case), my idea was to use a fixed clock for output from DP. My understanding was that in that case I simply always get data_valid which is intermittent during one line - which is fine by me. Am I wrong?

[Florent] - This will be the case but you would need a clock which is fast enough.

The timing in question (which produces error) is a custom modification - but speaking generally, I would like to have a solution which can adapt to any timing.

Best regards

Srdjan


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar watari
Scholar
282 Views
Registered: ‎06-16-2013

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic 

 

I assume that you want to use native video interface.

If you want to resolve only FIFO overflow issue without native video interface, I strongly suggest you to follow @florentw 's opinion.

 

If you want to use native video interface, you can choose the solution from the followings.

 

Plan 1) Reproduce recovery pixel clock with Mvid and Nvid and trcking variety Mvid and Nvid with reconfiguration of flactional PLL. (Refer VESA DisplayPort document.)

Plan 2) Reproduce recovery pixel clock with Mvid and Nvid without tracking. But you have to close reproduced clock frequency as much as possible. Also prepare enoguh large FIFO.

Plan 3) Use well known resolution. Horizontal, vertical and clock frequency are same as it. But active timing are different.

 

Update - MVid = 32359, NVid = 32768. We use line rate for clock reference in this calculation, right? In our case it is 5.4 Gbps.

 

BTW, if you want to confirm it, you have to share horizontal and vertical timing. These information are very important for DP.

 

Best regards,

Participant srdjan.opacic
Participant
227 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Hi @florentw ,

I'm waiting on results for 200 MHz, if this helps I could keep it as a permanent solution (althoughj it will increase power consumption).

Thanks

Srdjan

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Participant srdjan.opacic
Participant
225 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Hi @watari ,

One thing is not clear to me - if I have clock sufficiently fast, how can I get overflow in FIFOs? Is it something inherent to the native interface? I'm asking because I assumed native interface doesn't require a precise clock, just sufficiently fast one. If this is not the case, I probably should move from native to AXIS interface - it is just that this means rewriting a lot of logic.

Thanks

Srdjan

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Moderator
Moderator
224 Views
Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic ,

200Mhz is the maximum tested. If this works, I am sure you can try to decrease it to find the lower frequency working between 150 and 200Mhz


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
227 Views
Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow

HI @srdjan.opacic ,

If you have a clock which is fact enough, you shouldn't get a FIFO overflow. But you need to be 100% sure that the clock is fact enough.

I am not sure about the size of the FIFO but they might not be big enough to wait the blanking period if your clock is not precise enough


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar watari
Scholar
220 Views
Registered: ‎06-16-2013

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic 

 

First of all, sorry, I can NOT explain previous my explanation in DETAIL. Because it has some know-how for me.

Threfore I can only explain funtamental things.

 

> I assumed native interface doesn't require a precise clock, just sufficiently fast one.

 

As @florentw  already mentioned, if you have enough FIFO size, it works fine without any FIFO error. ex. empty and/or full issue.

However, in fact you are facing FIFO issue.

 

This means that you need to consider accumulated inaccuracy between ideal pixel clock frequency and real pixel clock frequency.

It causes FIFO overflow or empty issue.

So, I suggest you to implement clock tracking mechanism or to prepare enough large FIFO.

 

Best regards,

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Participant srdjan.opacic
Participant
168 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Hi @watari ,

This overflow happens inside IP, so I cannot influence the size of FIFO. Output from DP IP is not stalled, outputted at maximum speed. So, besides increasing the clock speed, there is not much that I can do :(.

Anyway, increasing the clock speed to 200 MHz decreased the probability of error drastically, but not removed it entirely. My customer also found several monitors which also have problems with this DP source :(. It seems that the source is simply problematic, no matter what we do.

Regards

Srdjan

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Participant srdjan.opacic
Participant
165 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Hi @florentw ,

I increased clock to 200 MHz, I'm 100% sure that this should be sufficient in reference to the line data rate. The probability of error decreased drastically, but it still happens occasionally. my customer also found some monitors which also have problems with this DP source - I have to assume that in the end, the source itself is problematic, causing occasional overflows in the FIFO allocated to the lane 1. I never saw any overflows on other lanes.

if there are no other options in IP that I can try, I guess I'm oput of options, do you agree?

Regards

Srdjan

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Scholar watari
Scholar
127 Views
Registered: ‎06-16-2013

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic 

 

If there is this matter in elastic buffer, I suggest you to make sure the following.

 

- Confirm Mvid, Nvid value. I suggest you to use DP protocol analyzer or ILA or software.

- Confirm SSC. If SSC is enable, I suggest you to turn off SSC on DP Source device.

- Make sure video timing. Is it suitable for DP Sink ? Enough elastic buffer size ?

 

Best regards,

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Moderator
Moderator
95 Views
Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow

Hi @srdjan.opacic ,

Yes, if the source is having issue, then it will be difficult to fix the issue inside your design. You would need to make more investigation to check that this is related to the FIFO and not a signal quality.

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: DP RX Subsystem FIFO overflow

HI @srdjan.opacic ,

Is everything clear for you on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant srdjan.opacic
Participant
52 Views
Registered: ‎08-21-2017

Re: DP RX Subsystem FIFO overflow

Hi @florentw ,

I'm still waiting on feedback from customer, sorry. I'll update this thread as soon as possible.

Best regards

Srdjan

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