UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor aubogdan
Visitor
283 Views
Registered: ‎02-06-2019

DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi,

I simulate DP Sink Core with 2 lanes and connect it with my TX DP controller.

I am trying to transfer next image in 1x and 2x lanes: 640×480×75Hz, RGB 8/24, STREAM_clk is 31.5 MHz, LS_clk is 162 MHz.

In the 1x  everything is OK.

But in the 2x on the output video interface I see strange picture on the waveform:

Within the output of one line, I see moments when rx_vid_enable signal becomes inactive for one clock cycle.

I attached this picture.

What is the reason for this signal behavior ?

Is this a possible FIFO overflow due to too slow stream clock?

Thank you.

rx_vid_enable in 2x mode.jpg

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
239 Views
Registered: ‎11-09-2015

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

HI @aubogdan 

Are you using the Xilinx Displayport Rx subsystem or Displayport 1.4 RX subsystem?

Fifo overflow might be a root cause but I would say this is the opposite. Your video clock is slightly over the pixel clock so the core is compensationg toogling the data_enable signal.

The way to tell if you had a FIFO overflow is by looking at the register values

Note that for most cases, the core expect to be in a frame buffer use case (you have a VDMA or video frame buffer connected after the core) with the video clock over the pixel clock.

If you want to use the core in non-frame buffer use case, it requires you to use an extenal clock which can meet the requirement of the DP standard. Refer to pg233:

DP.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
9 Replies
Moderator
Moderator
240 Views
Registered: ‎11-09-2015

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

HI @aubogdan 

Are you using the Xilinx Displayport Rx subsystem or Displayport 1.4 RX subsystem?

Fifo overflow might be a root cause but I would say this is the opposite. Your video clock is slightly over the pixel clock so the core is compensationg toogling the data_enable signal.

The way to tell if you had a FIFO overflow is by looking at the register values

Note that for most cases, the core expect to be in a frame buffer use case (you have a VDMA or video frame buffer connected after the core) with the video clock over the pixel clock.

If you want to use the core in non-frame buffer use case, it requires you to use an extenal clock which can meet the requirement of the DP standard. Refer to pg233:

DP.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor aubogdan
Visitor
232 Views
Registered: ‎02-06-2019

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi, @florentw !

Thank you for answer.

------

I use Xilinx DisplayPort v7.0 and configure it as Sink Core.

Am I right understand next things:

— that for 1x mode when I use the core in the non-frame mode the frequency ratio between video and pixel clock is equal 1, so I can see my picture on the RX side.

— But when I switch to 2x mode I need use clock from external PLL for video clock, according  the requirement of the DP standard ?

0 Kudos
Moderator
Moderator
222 Views
Registered: ‎11-09-2015

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

HI @aubogdan 

Please note that the LOGICORE DIsplayport IP is a discontinued IP.

Then I am not sure about what more you are taling about. If this is about the clock mode in reg 0x528, no this is not correct. The clock mode is set by TX but the RX core is not using it.

Whatever if the clock is in sync or async mode, the behaviour will be the same. If you do not have any buffer, the clock need to exactly match the pixel clock. If you have a frame buffer, you can set a faster clock (because you recreate the pixel clock + data later).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor aubogdan
Visitor
209 Views
Registered: ‎02-06-2019

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi @florentw !

I attached my clock scheme.

The pixel clock is the same for the TX and RX parts.

I don’t understand why it works in 1x mode, but not in 2x mode?

 

0 Kudos
Moderator
Moderator
205 Views
Registered: ‎11-09-2015

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi @aubogdan 

Again I do not understand what mode you are talking about. Please clarify.

Is it how many lanes are trained?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor aubogdan
Visitor
195 Views
Registered: ‎02-06-2019

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

@florentw 

2 lanes are trained.

The values from DCPD for Xilinx RX:

00001h - 06h (1.62 Gbps)

00002h - 2h (Two lanes)

---

I transfer the same image in 1x mode (I configured all system in 1 lane) - it works.

I do not understand why it is not work in 2x mode. The image and its parameters are the same as for 1x : 640×480×75Hz.

I hope you understand my question.

Thank you.

 

0 Kudos
Scholar watari
Scholar
181 Views
Registered: ‎06-16-2013

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi @aubogdan 

 

What kind of DP source device do you use ?

It depends on the result of negotiation between source and sink devices and architecture of graphics card's driver.

 

Best regards,

0 Kudos
Moderator
Moderator
166 Views
Registered: ‎11-09-2015

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

HI @aubogdan 

When moving to 2 lanes you need to make sure that all the parameters of the timing are dividable by 2. Also the pixel clock is divided by 2. You need to make sure you have the correct precision.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor aubogdan
Visitor
154 Views
Registered: ‎02-06-2019

Re: DP Sink Core with 2x lane and Native video interface

Jump to solution

Hi @florentw.

The input image is coming to TX part with the 35 MHz for the pixel clocks. If I divide it by 2, I'll have 17.5 MHz. But in the data sheet (page 11, PG064 November 30, 2016) I see that the minimum for the vid_clk is 25 MHz.

I am trying to do next:

1. Transfer the image, which really need 2x mode.

2. Use frame buffer for the Rx native video interface.

Thank you for answer.

I return with the Results.

0 Kudos