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Observer
Observer
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Registered: ‎03-23-2017

DPHY RX clock debug

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I'm using the MIPI DPHY 4.1 Rx core in Zynq Ultrascale+.  It works fine with some CSI image sensors, but I'm having clocking problems when using another SoC's MIPI DSI output as the source.  I'm trying to receive MIPI DSI from an SoC using a custom DSI receive core in combination with Xilinx's DPHY 4.1.

When I read the DPHY CL_STATUS register when using the CSI image sensor, I always get 09h.  When I read CL_STATUS from the DSI source, I get one of 28h, 29h, or 2eh.  It works enough so that I do get some images through, but very sporadically.  The clock looks like this:

It's bifurcating between an OK square wave and an unterminated mess whenever the DPHY turns the terminator off, which seems to be very often.

I've also included my DPHY settings.

I'm pretty sure the DSI source is using continuous clock mode- at least I can't trigger on the LP signal levels on the clock line.  Does DPHY work with continuous clock mode or am I seeing expected behavior for it?  Does anyone have any suggestions for getting this to work?

Thanks!

 

tek00003.png

 

dphy-settings.pngdphy-settings-1.png

Here is one more, showing when DPHY turned off terminator.  Notice on the zoomed out top, I'm not sure what's going on here.

 

tek00004.png

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Observer
Observer
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Registered: ‎03-23-2017

Re: DPHY RX clock debug

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And the problem was a PCB mistake- the ground side of the MIPI micro coax cables were connected to each other, but not to PCB / FPGA ground, oops.  The effect is that differentially it was OK, but massive cross-talk between single-ended signals such as the LP signaling.

With this fixed, the common system level problem I see others talk about on the forums is revealed.  DPHY is unhappy without seeing LP-11 during boot up.  We temporarily worked around this by adding pull-ups, letting DPHY boot with the MIPI cable disconnected, then plug in the cable and turn on the DSI source.  With this we get perfect video.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: DPHY RX clock debug

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Hello @jhallen 

MIPI D-PHY RX works with both continuous and non-continous clock mode.
Getting CL_STATUS = 0x29, or 0x2e is not expected when TX output continous clock mode.

1. What is the Vivado version ?
2. Are your SoC's MIPI DSI clock output is always toggling from the start ?
During MIPI D-PHY RX initialization period, could you please ensure that SoC output LP-11 ?
3. How do you feed 200MHz core_clk ? ( Is it from external OSC/PLL, or FPGA MMCM or PS clock ? )


Thanks
Leo

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Observer
Observer
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Registered: ‎03-23-2017

Re: DPHY RX clock debug

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Hi Leo,

Vivado version is 2019.1

200 MHz clock is from PS PLL (fed from external 33.33 MHz oscillator).  There are other DPHY TXs and RXs in the chip that are working fine from the same clock.

SoC is powered off from the start- I assume it's at least transitioning through LP-11, but I need to check this (tomorrow).  I'll try to get it into LP-11 during DPHY init, but not sure I have enough control over it (software support) yet.

If DPHY doesn't see LP-11 during init, what happens?  Will it recover if the SoC goes back to stop state?  I ask because if it can recover it may be more pratical to put it in discontinuous clock mode.

Can you tell me a little about the clock lane logic?  Will it exit HS mode based on what's happening from the other lanes, or only on what it sees on the clock lane?  I assume it's only looking at the clock lane..

Thanks,

Joe

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: DPHY RX clock debug

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Hello Joe @jhallen 

> Vivado version is 2019.1

Noted.
I do not notice/see any issue for 2019.1 MIPI D-PHY RX using UltraScale+ devices.

> 200 MHz clock is from PS PLL (fed from external 33.33 MHz oscillator).
> There are other DPHY TXs and RXs in the chip that are working fine from the same clock.

Well noted.

> SoC is powered off from the start- I assume it's at least transitioning through LP-11,
> but I need to check this (tomorrow).
> I'll try to get it into LP-11 during DPHY init, but not sure I have enough control over it (software support) yet.

Okay, Please share your scope shot tomorrow.

> If DPHY doesn't see LP-11 during init, what happens?
> Will it recover if the SoC goes back to stop state?
> I ask because if it can recover it may be more pratical to put it in discontinuous clock mode.

Ussualy INIT_DONE will not be asserted if LP-11 is not seen during initialization.
But I can see that clock lane INIT_DONE is asserted.
But since the behavior of the signal is not expected, I am wondering if the initialization process is expected.

> About the clock lane logic? Will it exit HS mode based on what's happening from the other lanes,
> or only on what it sees on the clock lane? I assume it's only looking at the clock lane..

I need to confirm but I believe clock lane logic only looking at clock input signal.

Questions
1. Would you be able to check the behavior of your custom SoCD if its output is connected to external resistor ?
    Do you see any signal level fluctuation ? Do you see the same behavior if SoC is not connected to UltraScale+ input pins ?
SoC_not_connected.png
2. Is SoC output line-rate and MIPI D-PHY RX line-rate the same ?
    ( Did you set the same line-rate on D-PHY RX GUI and generated the IP ? )


3. Would you be able to capture MIPI D-PHY RX internal signal ? (Please capture all the signal with free-run 200MHz core_clk )
         cl_rx_state
         cl_en_hs_rx_term
         lp_state_sync
         clk_active
         rst_seq_done
         vtc_rdy

 

Regards
Leo

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Observer
Observer
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Registered: ‎03-23-2017

Re: DPHY RX clock debug

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So I captured this:

tek00006.png

Yellow is clock lane as seen by a differential probe.  Blue is one leg of the clock lane as seen by a single-ended probe.  Magenta is one leg of one of the data lanes.  The horizontal rate of the DSI video is 50 KHz (explaining the transitions to LP every 20 us).

I don't understand the pulses on blue- maybe crosstalk from the other lanes when they go into LP mode?  It would explain why DPHY turns the terminator off- it could be seeing a false LP transition..   maybe the common mode impedance when the terminators are on is high, but even if so I find it hard to believe that there is so much crosstalk.  We are using microcoax cables between the SoC board and the FPGA board and of course differential traces and proper ground planes.

We tried your experiment no. 1, with just a terminator, no FPGA (we had some boards without the expensive FPGA to verify the power supply, so this was pretty easy to do):

Clock is fine (this is infinite persistence):

tek00008.png

 

But also we don't see the crosstalk as much without the FPGA, not sure why not.

tek00007.png

 

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Observer
Observer
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Registered: ‎03-23-2017

Re: DPHY RX clock debug

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And the problem was a PCB mistake- the ground side of the MIPI micro coax cables were connected to each other, but not to PCB / FPGA ground, oops.  The effect is that differentially it was OK, but massive cross-talk between single-ended signals such as the LP signaling.

With this fixed, the common system level problem I see others talk about on the forums is revealed.  DPHY is unhappy without seeing LP-11 during boot up.  We temporarily worked around this by adding pull-ups, letting DPHY boot with the MIPI cable disconnected, then plug in the cable and turn on the DSI source.  With this we get perfect video.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: DPHY RX clock debug

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Hello Joe @jhallen 

>ground side of the MIPI micro coax cables were connected to each other, but not to PCB / FPGA ground, oops.

I see. Thank you for debugging this issue.

>DPHY is unhappy without seeing LP-11 during boot up. We temporarily worked around this by adding pull-ups, letting DPHY boot with the MIPI cable disconnected, then plug in the cable and turn on the DSI source. With this we get perfect video.

I see. Yes MIPI D-PHY RX is unhappy.
As MIPI D-PHY specification mentioned that LP-11 is required during initialization.
BTW, MIPI D-PHY RX has INIT_VAL=100us as default value. You might want to set to smaller value, if your SoC cannot output LP-11 more than 100us.


Regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: DPHY RX clock debug

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Hello Joe @jhallen 

Could you please kindly mark this post as solved ?
So other forum users can learn from your debug result.

Thanks & regards
Leo