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Visitor nickthequik
Visitor
2,079 Views
Registered: ‎10-15-2017

Debugging Scaler-Only Video Processing Subsystem

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I am trying to get the Video Processing Subsystem in scaler only mode to scale a 1280x1024 frame coming from the Test Pattern Generator down to 1024x768 which is being output to the AXI-Stream to Video Out block. I have the Video Processing Subsystem configured in Scaler Only mode with the Bicubic interpolation algorithm. I am using a Zynq 7010 SoC.

 

I have been breaking out the AXI-Stream handshake signals between the TPG and Video Processing Subsystem to try to understand what is going on. So far, I have noticed that there are 2 complete line transfers that seem to complete with both the TPG asserting VALID and the Video Processing Subsystem asserting READY. However, during the transmission of the third line of the frame, the Video Processing Subsystem deasserts its READY signal. Afterwards, the READY signal is only briefly pulsed for some time before stopping completely. I have included a picture of my scope capture below.

 

VPS-TPG AXI-Stream Handshake

 

Here is a screencap of the setup I have in the Vivado block design.

 

vps.PNG

 

I'm really not sure what is wrong in this case. I am using modified code from the Xilinx examples to instantiate the Video Processing subsystem. I have already verified the TPG and Video Out blocks work together. The problem seems to be that the Video Processing Subsystem is entering a weird state in which is deasserts READY which essentially stops all transactions.

 

Here is the code I am using to initialize the Video Processing Subsystem:

 

typedef struct {
u16 width_in;
u16 height_in;
XVidC_ColorFormat Cformat_in;
u16 IsInterlaced;
u16 width_out;
u16 height_out;
XVidC_ColorFormat Cformat_out;
} vpssVidio;

typedef enum
{
XSYS_VPSS_STREAM_IN = 0,
XSYS_VPSS_STREAM_OUT
}XSys_StreamDirection;

void XSys_SetStreamParam(XVprocSs *pVprocss, u16 Direction, u16 Width, u16 Height,
XVidC_ColorFormat cfmt, u16 IsInterlaced);

XVprocSs vprocss;
vpssVidio thisCase;

void VPSS_init(void) { int status; XVprocSs_Config* vprocss_config; vprocss_config = XVprocSs_LookupConfig(XPAR_V_PROC_SS_0_DEVICE_ID); if(vprocss_config == NULL) while(1); /* Start capturing event log. */ XVprocSs_LogReset(&vprocss); memset(&vprocss, 0, sizeof(XVprocSs)); status = XVprocSs_CfgInitialize(&vprocss, vprocss_config, vprocss_config->BaseAddress); if(status != XST_SUCCESS) while(1); thisCase.width_in = 1280; thisCase.height_in = 1024; thisCase.Cformat_in = XVIDC_CSF_RGB; thisCase.IsInterlaced = FALSE; thisCase.width_out = 1024; thisCase.height_out = 768; thisCase.Cformat_out = XVIDC_CSF_RGB; //Stream In XSys_SetStreamParam(&vprocss, XSYS_VPSS_STREAM_IN, thisCase.width_in, thisCase.height_in, thisCase.Cformat_in, thisCase.IsInterlaced); //Stream Out XSys_SetStreamParam(&vprocss, XSYS_VPSS_STREAM_OUT, thisCase.width_out, thisCase.height_out, thisCase.Cformat_out, thisCase.IsInterlaced); status = XVprocSs_SetSubsystemConfig(&vprocss); //Query video processing subsystem configuration XVprocSs_ReportSubsystemConfig(&vprocss); XVprocSs_ReportSubcoreStatus(&vprocss, XVPROCSS_SUBCORE_SCALER_V); XVprocSs_ReportSubcoreStatus(&vprocss, XVPROCSS_SUBCORE_SCALER_H); XVprocSs_LogDisplay(&vprocss);

void XSys_SetStreamParam(XVprocSs *pVprocss, u16 Direction, u16 Width, u16 Height,
XVidC_ColorFormat cfmt, u16 IsInterlaced)
{
XVidC_VideoMode resId;
XVidC_VideoStream Stream;
XVidC_VideoTiming const *TimingPtr;

resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_60HZ, IsInterlaced);
TimingPtr = XVidC_GetTimingInfo(resId);

//Setup Video Processing Subsystem
Stream.VmId = resId;
Stream.Timing = *TimingPtr;
Stream.ColorFormatId = cfmt;
Stream.ColorDepth = pVprocss->Config.ColorDepth; // Check that this gets set
Stream.PixPerClk = pVprocss->Config.PixPerClock; // Check that this gets set
Stream.FrameRate = XVIDC_FR_60HZ;
Stream.IsInterlaced = IsInterlaced;

if(Direction == XSYS_VPSS_STREAM_IN)
{
XVprocSs_SetVidStreamIn(pVprocss, &Stream);
}
else
{
XVprocSs_SetVidStreamOut(pVprocss, &Stream);
}
}

 

 Any thoughts or suggestions would be appreciated!

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Visitor nickthequik
Visitor
2,708 Views
Registered: ‎10-15-2017

Re: Debugging Scaler-Only Video Processing Subsystem

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I increased the max number of pixels and max number of lines in the IP customization block and now it works...

 

I'm assuming this somehow made the buffers bigger which allowed the correct amount of lines to be captured so that the scalers could actually work. Previously, I had the max number of pixel set to 1280 and max number of lines to 1024 which was the exact same size as my input frame.

 

Solution: Make your buffer bigger than your input frame.

 

Why this works still does not makes sense and should be addressed in the documentation.

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5 Replies
Moderator
Moderator
2,036 Views
Registered: ‎11-09-2015

Re: Debugging Scaler-Only Video Processing Subsystem

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HI @nickthequik,

 

The problem seems to be that the Video Processing Subsystem is entering a weird state in which is deasserts READY which essentially stops all transactions

Are you always using the same resolution? Are you stopping the stream at some point? Re configuring the TPG? If yes the VPSS needs to be restarted each time.

 

Hope that helps,

 

Regards

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor nickthequik
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2,024 Views
Registered: ‎10-15-2017

Re: Debugging Scaler-Only Video Processing Subsystem

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The Streams that are shown in the code are the only resolutions that the VPS are initialized with. I never change any settings after initializing the VPS. My init sequence is VPS, VTC, and then TPG.

 

When you say reset, I am assuming you mean the internal "software" restart which is triggered by a register write as opposed to a hardware reset at the aresetn input. This software reset seems to occur twice throughout the initialization of the VPS but it is being called by the driver functions.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Debugging Scaler-Only Video Processing Subsystem

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Hi @nickthequik,

 

Yes I meant the SW reset.

 

Did you checked the tready at the output of the VPSS (from the video out IP)?

 

To investigate more, you might want to use the following functions:

XVprocSs_ReportSubcoreStatus()

XVprocSs_LogDisplay()

 

You can find more information about them in the API

<Xilinx installation path>\SDK\2017.3\data\embeddedsw\XilinxProcessorIPLib\drivers\vprocss_v2_4\doc\html\api

 

FYI, this is unlikely that this is causing the issue but I see that you are using a custom IP from the VPSS to the video out IP. You also could have used the AXI-Stream Subset converter IP.

 

Also I don't know which design example you tried, but there should be one example for the VPSS (using the TPG) integrated in vivado (right click on the source window > generate example design)

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor nickthequik
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Registered: ‎10-15-2017

Re: Debugging Scaler-Only Video Processing Subsystem

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When I try the example project, I get the following error

error.PNG

 

Here is the printout from the functions:

 

XVprocSs_ReportSubsystemConfig(&vprocss);
XVprocSs_ReportSubcoreStatus(&vprocss, XVPROCSS_SUBCORE_SCALER_V);
XVprocSs_ReportSubcoreStatus(&vprocss, XVPROCSS_SUBCORE_SCALER_H);
XVprocSs_LogDisplay(&vprocss);

 

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
3D Format: Field Alternative
Frame Rate: 60Hz
Resolution: 1280x1024@60Hz
Pixel Clock: 107964480

->OUTPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
3D Format: Field Alternative
Frame Rate: 60Hz
Resolution: 1024x768@60Hz
Pixel Clock: 64995840

 

----->V SCALER IP STATUS<----
IsDone: 0
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Scaler Type: Bicubic
Input Width: 1280
Input Height: 1024
Output Height: 768
Line Rate: 87381
Num Phases: 64


----->H SCALER IP STATUS<----
IsDone: 0
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Scaler Type: Bicubic
Input&Output Height: 768
Input Width: 1280
Output Width: 1024

4:2:2 processing: Disabled
Color Format: RGB
Pixel Rate: 81920

Num Phases: 64

 

VPSS log
-----------
Info: Subsystem start init
Info: Topology is Scaler-only
Info: Reset_AxiS init
Info: HScaler init
Info: VScaler init
Info: Subsystem reset
Info: Subsystem ready
Info: Subsystem configuration is valid
Info: Scaler-only configuration is valid
Info: Subsystem reset
Info: Scalers start
log end
-----------

 

I'm not sure what the IsDone, IsReady, and IsIdle fields imply as there is no documentation describing what they mean.

 

The Video Out READY signal is asserted for all time except for when the VPSS block is resetting it. The VPSS VALID signal is never asserted. Therefore, no transaction between the VPSS and Video Out is occurring. 

 

What could cause the VPSS to deassert its READY signal? A full input buffer? Is there any way to tell if the scalers are actually functioning?

 

I know the scaler is broken up into a vertical and horizontal scaler. If the Bicubic algorithm is using 4x4 tap as stated in the documentation, it needs 4 full lines before it can output anything. This explains why it is not outputting anything as it is never getting past the last bit of the 3rd line in the frame.

 

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Visitor nickthequik
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2,709 Views
Registered: ‎10-15-2017

Re: Debugging Scaler-Only Video Processing Subsystem

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I increased the max number of pixels and max number of lines in the IP customization block and now it works...

 

I'm assuming this somehow made the buffers bigger which allowed the correct amount of lines to be captured so that the scalers could actually work. Previously, I had the max number of pixel set to 1280 and max number of lines to 1024 which was the exact same size as my input frame.

 

Solution: Make your buffer bigger than your input frame.

 

Why this works still does not makes sense and should be addressed in the documentation.

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