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Registered: ‎01-21-2019

Deinterlacer Algorithm Selection, Revisited

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Reference:  https://forums.xilinx.com/t5/Video/Deinterlacer-Algorithm-Selection/m-p/872954#M20933

In this older post (link above), the deinterlacer algorithm was not settable. It looks like the next month, the IP was changed so that the algorithm could be set but only during configuration and before the deinterlacer start.

I am using the Deinterlacer within VPSS using Vivado 17.4.

We have been unable to get the deinterlacer to work at all and only once did we get the bypass to work but we could not duplicate how we accomplished this monumental feat. :)

I have never been able to set the Deinterlacer Algo during set up time. No error but the Deint always reverted to 0 when checked.  However, after XVprocSs_SetSubsystemConfig(), I was able to set the Algo properly, according to XV_DeintDbgReportStatus() but the resulting output image appeared to be the same (not good). As you can tell, we are using the SDK.

We are not able to get the Deinterlacer to work and I am thinking that we are overrunning the Deint. I was hoping to reduce the load of the Deint by changing the Algo to something like Bob (1) with less intensive compute/memory requirements to speed up the processing time. But, I don't think the Algo is having much effect on the output.  See status message below.

Is it possible that the Algo is not actually being set?

Thanks.

Phil

----->Deinterlacer IP STATUS<----
IsDone: 0
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Read Frame Buffer: 0x80000000
Write Frame Buffer: 0x80000000
Color Format: 0
Algo Selected: 1
Width : 1920
Height : 540

 

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Moderator
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Registered: ‎11-09-2015

Re: Deinterlacer Algorithm Selection, Revisited

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Hi phil@pswitchers.com 

The algorithm version is mentioned in the latest version of the doc (May 22, 2019)

VPSS.JPG

 

Note that the pass-through option is only there since 2018.3 but the driver was not supporting it. In 2019.1 you should be able to use the VPSS configured as deinterlacer only and use the pass-through.

Thank you for sharing the steps for changing the algorithm. This is not the best, I will request to have a higher level API to change it when starting the core or changing the stream.

If everything is clear for you on this topic, can you kindly mark it as solved to close it?

Thanks and Regards

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Deinterlacer Algorithm Selection, Revisited

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HI phil@pswitchers.com ,

As per this topic, this is in my plan to create an example but I am not sure when I will be able to complete it.

I think the algorithm is properly set in your case. But you will not see any effect of the latency of the core which is probably what the bottleneck is.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎01-21-2019

Re: Deinterlacer Algorithm Selection, Revisited

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@florentw ,

Here is the trick we learned to change the Algorithm.

The API routine, XV_deinterlacer_Set_algo() should be run right after the the XVprocSs_CfgInitialize() and before the XVprocSs_SetSubsystemConfig(). If you set this Algo in any other order then the Algo routine is ignored and returns to 0 (Median).

Additionally, the value associated with the algorithm is not defined in the manual. I found these values in another forum post. Here are the defines I created to support these algorithms:

// Deinterlacer Algorithms
#define ALGO_MEDIAN 0 // Median
#define ALGO_BOB 1 // Bob (Linear Interpolation) "Line Doubling Mode"
#define ALGO_WEAVE 2 // Weave
#define ALGO_VERT_TEMP_LINEAR 3 // Vertical Temporal Linear Interpolation (VTLin)
#define ALGO_VERT_TEMP_MEDIAN 4 // Vertical Temporal Median
#define ALGO_PASS_THRU 6 // Bilinear Pass Through Mode

If one creates a VPSS with Deinterlacer only, the Deinterlacer will not pass through progressive video. It will fail in an error message. Bypassing the error message will also fail. A full VPSS configuration will bypass the deinterlacer with the internal switch/router but a Deinterlacer only configuration does not include a bypass mechanism for signals not using the deinterlacer.

I do not see any evidence that the deinterlacer works any faster in Bob mode. We still appear to be overrrunning the deinterlacer with a 1080i@60 video stream.

We are also watching the forum post by others experiencing the same problem:  https://forums.xilinx.com/t5/Video/VPSS-pipeline-and-Deinterlacer-causing-problems/m-p/983075#M25794

Thank you, @florentw 

Phil

Moderator
Moderator
329 Views
Registered: ‎11-09-2015

Re: Deinterlacer Algorithm Selection, Revisited

Jump to solution

Hi phil@pswitchers.com 

The algorithm version is mentioned in the latest version of the doc (May 22, 2019)

VPSS.JPG

 

Note that the pass-through option is only there since 2018.3 but the driver was not supporting it. In 2019.1 you should be able to use the VPSS configured as deinterlacer only and use the pass-through.

Thank you for sharing the steps for changing the algorithm. This is not the best, I will request to have a higher level API to change it when starting the core or changing the stream.

If everything is clear for you on this topic, can you kindly mark it as solved to close it?

Thanks and Regards

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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