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Newbie ggrummer
Registered: ‎03-17-2017

Deinterlacer Startup Sequence

Does anyone have a startup sequence for the Video In to AXIS and Deinterlacer IPs?  I'm using Deinterlacer version 4.0 (3.x should work too).  I have the Video In to AXIS IP connected to a bug fix module which connects to the Deinterlacer.  The Deinterlacer's master tdvalid is tied to master tready.  Tieing master tready high doesn't work.


The bug fix module provides one tuser (SOF) pulse per frame (to the Deinterlacer) and enables tready (to the Video In to AXIS) until the first tuser pulse (from the Video In to AXIS) then forwards the Deinterlacer's tready.  Are there other fixes I'm missing?


I can't get the Deinterlacer to output anything.  Most of the time the Deinterlacer prevents the Video In to AXIS from outputting.  I've tried different combinations of resets and enables and register settings, but can't come up with a functioning combination.

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Xilinx Employee
Xilinx Employee
Registered: ‎05-07-2015

Re: Deinterlacer Startup Sequence

HI @ggrummer


The old Deinterlcaer 4.0 core is currently deprecation  and  the new Video processing subsystem is to replace most of the old standalone cores.
please use the VPSS IP in de-interlacer only mode.

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