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1,679 Views
Registered: ‎12-24-2017

Direct memory access through VDMA and DMA

Hi, Currently I am working on a project of video processing. I want to do background subtraction of a video stream. Therefore, I use Video Direct Memory Access(VDMA) xilinx AXI IP core and Direct Memory Access(DMA) xilinx IP core to take a current video stream and the reference image. Simple idea is to subtract reference image from the current frame.

 

I use AXI interconnect to connect all IPs into one system. My video stream is Full HD (1920x1080), 60 fps. I use zedboard to integrate the system and I access to DDR3 through zynq processing system. My problem is can I do this(I am asking this because I didn't get my expected result, and I have doubt of my plan)?

Currently, I am trying to do this by only using HP ports available in sync system. Do I have to use Accelerator Coherency Port(ACP) to let zynq to manage cache coherency? What gain I can get using ACP port?

It is very kind of you if anyone can guide whether my project is feasible and let me know gain I get using ACP port.

Thank in advance.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Direct memory access through VDMA and DMA

@omegaishendra  The advantage of using the ACP is that the data will be available to the ZYNQ in the cache. With the HP ports, you will have to invalidate the cache manually.

However as the image is large, using the ACP will kill the Zynq cache so I dont' think there will be any benefit.

Using the HP ports in this case is the right thing to do.

 

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1,622 Views
Registered: ‎12-24-2017

Re: Direct memory access through VDMA and DMA

Thank you very much for the reply. what do you mean by kill cache? What I understood is, although image size is large, due to caching I would be able to get some advantage of quick data retrieving. However my what my biggest problem is;  Can AXI bus be able to handle both vdma and dma data streams parallel.

That means I have doubt of how the storing in DDR3 memory happens.

1)First store image from VDMA in continuous memory locations and then from DMA?

 Or

2)Can we store part of the image from vdma(say one row of the image) then part of the image from vdma?

 

I want to get corresponding data from vdma and dma at the same time.

 

Thank you

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Direct memory access through VDMA and DMA

@omegaishendra  You should check the maximum bandwidth of your DDR memory and use that to estimate the minimum time to store a matrix in it. For example, DDR4-2600 has a maximum write bandwidth around 5 Gbps or 625 MBytes/s. One 1920x1080 RBG image is 6.22 MBytes which gives you around 100 frames/second - without any processing. Add to that all the calculations and pushing the entire image back then you see that DDR is really not feasible for realtime video processing.  More often, the image is stored and processed in the PL-side block RAM, when available.

 

The cache will give you an advantage on small items accessed repeatedly. There is no benefit from large items accessed sequentially - in this case the result would be evicting all the CPU cache lines which will lower the software speeds.

 

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Registered: ‎12-24-2017

Re: Direct memory access through VDMA and DMA

@hbucher

thanks again for the reply. I understand your logic but I have somewhat different experience for that. I was able to integrate vdma to store and retrieve video stream using zed board for above mention resolution and frame rate. DDR3 of zedboard is used as a triple frame buffer(store 3 frames) and It is said that zedboard ddr3 has only 1066 Mbps bandwidth.

Since it is very low bandwidth I doubt that how it happened now. However I was able to get full hd 60 fps video and display it in monitor real-time! I used 148.5MHz for the implementation to maintain 1080p, 60fps and video timing controller which is used to display video is confgured to 1080p constant mode.

 

So, can you please explain me how that happen contrast to our calculation? Thank again for keep replying me.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Direct memory access through VDMA and DMA

@omegaishendra I have no idea - it is your system. You tell me. I am just making back-of-napkin calculations.

I got 100 fps and you got 60 fps so it looks like you are not doing much processing such that DDR is just enough to keep up.

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1,586 Views
Registered: ‎12-24-2017

Re: Direct memory access through VDMA and DMA

thanks for the reply.

In my system, I was able to write 60 frames to the DDR and read 60 frames from DDR and display those in monitor realtime. So totally 120 frames are handled by DDR. That was my confusion.

Anyway what my main concern is when we use vdma and dma at the same time to read different memory locations, will it let one of them to complete their whole transaction and after that allow other one to complete its transaction or will it let one of them to transfer some amount, then allow another one to transfer some amount and again transfer some amount and let other one...so on?

what would be the way vdma and dma work?

Thank you very much if you can clarify me this.

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Moderator
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Registered: ‎11-09-2015

Re: Direct memory access through VDMA and DMA

HI @omegaishendra,

 

Anyway what my main concern is when we use vdma and dma at the same time to read different memory locations, will it let one of them to complete their whole transaction and after that allow other one to complete its transaction or will it let one of them to transfer some amount, then allow another one to transfer some amount and again transfer some amount and let other one...so on?

what would be the way vdma and dma work?

-> It depends on how you have built your system. You can have many case. One could have trhe priority, then could be reading at the same time etc...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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1,341 Views
Registered: ‎11-09-2015

Re: Direct memory access through VDMA and DMA

Hi @omegaishendra,

 

Is everything clear for you? If you do not have more questions related to this, please kindly mark a response as solution to close the topic.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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