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Registered: ‎08-31-2016

Display Port TX Design requirements

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Hi,

 

Is there any DP TX only example design based on Zynq PS running with linux?

I'm targeting Zynq MPSOC 7EV device.

 

Also, What is the GT TX reference clock to be given to achieve 4K @60fps resolution across DP output?

 

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

I used the example designs integrated in vivado + sdk. Nothing more.

Please try with the DP 4K monitor instead of using an adapter.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar watari
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy

 

> Is there any DP TX only example design based on Zynq PS running with linux?

 

Refer the following a).

 

> Also, What is the GT TX reference clock to be given to achieve 4K @60fps resolution across DP output?

 

It depends on color depth and video timing. (VESA CVT or CEA ?)

However, you might be able to output 4K@60Hz by reduced blank.

 

[FYI]

a) Xilinx Wiki

http://www.wiki.xilinx.com/ZynqMP+DisplayPort+Linux+driver

 

b) AR #71499

https://www.xilinx.com/support/answers/71499.html

 

Best regards,

Moderator
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Re: Display Port TX Design requirements

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HI @vinay_shenoy,

 

As mentioned by @watari you can use the example design from a). However, you won't be able to reach 4K60 as it is using the harden displayport controller which has only 2 GT connected. As it is DP1.2, you will be only able to support 4K30 with the harden controller.

 

The only way to do 4K60 would be to use the soft IP (Displayport TX Subsystem IP). You can use the DP1.2 or DP1.4 IP. For new design I would recommend the DP1.4 IP even if you wish to run only DP1.2 rates. The example design are mentioned in the corresponding PG. However, there are no linux driver for the displayport subsytem IP yet. If you have enough motivation you can write the linux driver yourself. My recommendation is to contact your FAE to discuss about the best solution for your project. And he could contact marketing to see if there is any plan to have the linux drivers.

 

To clarify @watari replies on 4K@60Hz with reduced blank it is because, as per the DP spec, you do not have enough BW to do RGB/YUV444 4k60 without having the reduced bandwidth.

 

@watari: Thank you for your reply that was good. Sorry I had to clarify a bit ;)


Florent
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Re: Display Port TX Design requirements

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Thank you @watari and @florentw.

 

I appreciate your detailed explanation. I was in search of fully functional DP TX example design that I could use as base for my custom design with 7EV device. From PG199, I was able to generate the SDK based DP TX design. However, I don't see much explanation about the design settings, limitations, functions supported in the example design chapter of product guide. 

 

All I want here is to test DP output at 4K (UHD) @60fps. 

@watari As I follow PG199, It supports UHD @60fps and implements VESA v1.2a.

Planning to have RGB format with 8 bit color depth & have set the Max. Lane rate to 5.4 Gbps in phy controller. Could you now suggest me possible GT Ref. clk need for this design to work?

 

 

 

 

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy

 

In your case, I suggest to refer example design which is generated by yourself on Vivado.

However, this design is not for MPSoC.

But PL fabric is same as Ultra Scale+ FPGA.

 

Would you refer it ?

 

Best regards,

 

Moderator
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Re: Display Port TX Design requirements

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HI @watari and @vinay_shenoy

 

My replies:


@watari wrote:

Hi @vinay_shenoy

 

In your case, I suggest to refer example design which is generated by yourself on Vivado.

However, this design is not for MPSoC.

But PL fabric is same as Ultra Scale+ FPGA.
[Florent] - It depends what you call MPSoC. This is true if you just talk about the harden controller. If you are talking about MPSoC in general, there is a design for it. There is a TX-only and Rx-only design for ZCU102. Note that you require a FMC card for that. The on board DP connector is only for the DP controller from the PS.

 

 

Would you refer it ?

 

Best regards,

 


 

 


@vinay_shenoy wrote:

Thank you @watari and @florentw.

 

I appreciate your detailed explanation. I was in search of fully functional DP TX example design that I could use as base for my custom design with 7EV device. From PG199, I was able to generate the SDK based DP TX design. However, I don't see much explanation about the design settings, limitations, functions supported in the example design chapter of product guide. 

[Florent] - What do you mean? The example design should should all the features of the DP IP. So just refer to the rest of the PG. All the limitations and features are applicable to the PG. There is only a limitation on the bit per component but this is mentioned in table 5-1

 

@All I want here is to test DP output at 4K (UHD) @60fps. 

@watari@ As I follow PG199, It supports UHD @60fps and implements VESA v1.2a.

Planning to have RGB format with 8 bit color depth & have set the Max. Lane rate to 5.4 Gbps in phy controller. Could you now suggest me possible GT Ref. clk need for this design to work?

[Florent] - Again, if you need to test in on an evaluation board you will need an FMC card from inrevium. Do you have one? You will not be able to do 4k60 with the on-board DP connector as per limitation mentioned earlier

For the reference clock, a single 270MHz is required for all resolutions supported per the DP1.2 spec.

 


 


Florent
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Re: Display Port TX Design requirements

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Hi @florentw

 

I don't have an FMC here. Could you suggest me any DP TX design that I can use for my custom board design?

I have a DP output in my custom board. I'd prefer a PL design having SDK source files.

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

You can still use the ZC102 TX only example design as a reference. This is the better start. But you will still have to do some modification to the HW and maybe the application.

 

Also, note that Xilinx only supports DP TX solutions using a DP130 redriver.

 

 


Florent
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Re: Display Port TX Design requirements

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Hi @florentw,

 

I have got couple of queries now.

 

1) Could you let me know what are the design HW changes to be done?

I have on-board GT Ref. Clk source here.

 

Also, I do see many RX related stuffs in the SDK application generated (Imported SDK example ie., xdptss_zcu102_dp14_tx)

What are these for?

 

2) Do you know why only DP130 redriver is being supported? 

What do you think about below redriver,

http://www.ti.com/lit/ds/symlink/sn65dp141.pdf . Can I make the design work with this?

 

 

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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HI @vinay_shenoy,

 

My replies:


@vinay_shenoy wrote:

Hi @florentw,

 

I have got couple of queries now.

 

1) Could you let me know what are the design HW changes to be done?

I have on-board GT Ref. Clk source here.

[Florent] - It should mainly be changing the part and the pin locations. But I might miss something

 

Also, I do see many RX related stuffs in the SDK application generated (Imported SDK example ie., xdptss_zcu102_dp14_tx)

What are these for?

[Florent] - Make sure to generate the TX only application for ZCU102. I do not see a lot of RX related stuff in xdptxss_zcu102_dp14_tx. There are some but it is just because the VPHY requires it. You should not need to remove any.

 

2) Do you know why only DP130 redriver is being supported? 

What do you think about below redriver,

http://www.ti.com/lit/ds/symlink/sn65dp141.pdf . Can I make the design work with this?

 [Florent] - The DP130 is the only one tested by Xilinx. Xilinx passes compliance only with the DP130. Thus it is the only one proved working. Other might work but it is up to the user to do their own characterization.

 

 


 


Florent
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Re: Display Port TX Design requirements

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Hi @florentw @watari

 

Thank you for your inputs. I was able re-target the design and test the DP output 4K@30. However, I wasn't able to test 4K@60 with reduced blank.

 

Getting this message "StreamBandwidth=399, LinkBandwidth=270, Over subscription and can't display"

 

Complete Test Log 

- - - - - - - - - - - - - - - - - - - - - - - -
- DisplayPort TX Only Demo Menu -
- Press 'z' to get this main menu at any point -
- - - - - - - - - - - - - - - - - - - - - - - - -
1 - Change Resolution
2 - Change Bits Per Color
3 - Change Number of Lanes, Link Rate
4 - Change Pattern
5 - Display MSA Values for Tx
6 - Change Format
7 - Display Link Configuration Status and user selected resolution, BPC
8 - Display DPCD register Configurations
9 - Read Auxiliary registers
a - Enable/Disable Audio
d - Power Up/Down sink
e - Read EDID from sink
m - Read CRC checker value
z - Display this Menu again
- - - - - - - - - - - - - - - - - - - - - - - - -
You have selected command 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- Select an Option for Resolution -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 640x480_60_P | 1 720x480_60_P | 2 800x600_60_P
3 1024x768_60_P | 4 1280x720_60_P | 5 1600x1200_60_P
6 1366x768_60_P | 7 1920x1080_60_P | 8 3840x2160_30_P
9 3840x2160_60_P | a 2560x1600_60_P | b 1280x1024_60_P
c 1792x1344_60_P | d 848x480_60_P | e 1280x960
f 1920x1440_60_P | i 3840x2160_60_P_RB | j 3840x2160_120_P_RB
k 7680x4320_24_P | l 7680x4320_30_P | m 3840x2160_100_P
n 7680x4320_30DELL| o 5120x2880_30 | p 7680x4320_30_MSTR
q 5120x2880_MSTR | r 3840x2160_120_MSTR
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Press 'x' to return to main menu
Press any key to show this menu again
You have selected command 'i'

Setting resolution...

Training TX with: Link rate 14, Lane count 4
.......^^...done !
- - - - - - - - - - - - - - - - - - - - - - - -
- DisplayPort TX Only Demo Menu -
- Press
'z' to get this main menu at any point -
- - - - - - - - - - - - - - - - - - - - - - - - -
1 - Change Resolution
2 - Change Bits Per Color
3 - Change Number of Lanes, Link Rate
4 - Change Pattern
5 - Display MSA Values for Tx
6 - Change Format
7 - Display Link Configuration Status and user selected resolution, BPC
8 - Display DPCD register Configurations
9 - Read Auxiliary registers
a - Enable/Disable Audio
d - Power Up/Down sink
e - Read EDID from sink
m - Read CRC checker value
z - Display this Menu again
- - - - - - - - - - - - - - - - - - - - - - - - -

==========power down===========

==========power up===========
StreamBandwidth=399, LinkBandwidth=270
Over subscription and can't display

 

 

Could you suggest any way I can check DP output at 4K@60?

 

Regards,

Vinay

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

Could you check that you are using 8bit per color (option 2 in the menu). It might be failing because you are using 10 bpc


Florent
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Re: Display Port TX Design requirements

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Hi @florentw

 

I've checked for 8bit per color only.

 

 

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy

 

Do you know "VESA COORDINATED VIDEO TIMING GENERATOR Revision 1.2" ?

Od, did you use it to calculate reduced blanking for 4K@60Hz ?

 

In my environment, DP Tx can output 4K@60Hz on KC-705. (*1)

 

*1)

I used example design for DP Rx and Tx on KC-705.

But this information is helpful for you.

 

Best regards,

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Re: Display Port TX Design requirements

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Hi @watari

No, I had just selected the application option available for 4K@60 reduced blank. ie., option i 3840x2160_60_P_RB.

Should I use the this timing generator to get RB values and update them manually in the SDK application?
Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

There might be an issue with the example design. The LinkBandwidth value you are getting seems to indicate that the application thinks your are trained at 2.7Gbps while the log file says that the link is trained at 5.4Gbps (link rate = 0x14).

 

I will investigate on this.

 

Regards,


Florent
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Re: Display Port TX Design requirements

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Hi @florentw

 

I have attached the AUX register value logs after setting 3840x2160 @60Hz (RB) for your reference.

 

Please let me know your inputs.

 

Regards,

Vinay

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Re: Display Port TX Design requirements

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Hi @vinay_shenoy

 

I confirmed DPCD value from you.

 

Almost all is fine. But it has a little strenge.

 

> Value at address offset 0x108, is = 0x0

 

This value means that main link channel coding set is not ANSI 8B10.

(It might be "Manchester II coding" ???)

 

I don't know why it was set. But I guess this value is caused by your problem.

 

[Edited (Add a content)]

> Getting this message "StreamBandwidth=399, LinkBandwidth=270, Over subscription and can't display"

 

I think that native streaming clock, which seems 399[MHz] (2 pixel per clock ?), is a little strange.

It might be hint to resolve this issue.

 

[Note (Additional Information)]

> Value at address offset 0x6, is = 0x1

 

This means that sink device supports ANSI 8B/10.

 

Best regards,

 

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Re: Display Port TX Design requirements

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HI @vinay_shenoy,

 

From the AUX log you are sharing, I do not see the the message as previously (StreamBandwidth=399, LinkBandwidth=270
Over subscription and can't display). You were still not getting any output from the monitor?

 

I tried to use the application with a 4K monitor and I was not able to reproduce the error you are getting. Howerver, what I noticed is that the value printed in "Training TX with: Link rate x, Lane count x" is what the core tries to train but not what the core is actually trained at. Can you try to add the following printf at the end of the start_tx function to see at what rate/lane you are trained:

 

    xil_printf ("..done !\r\n");

    xil_printf ("\r\nTX Trained with: Link rate %x, Lane count %d\r\n",
            DpTxSsInst.DpPtr->TxInstance.LinkConfig.LinkRate,
            DpTxSsInst.DpPtr->TxInstance.LinkConfig.LaneCount);

        return XST_SUCCESS;

 

Regards,


Florent
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

Do you gave any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
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Re: Display Port TX Design requirements

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Hi @florentw

 

After some changes, I am not seeing the earlier message "StreamBandwidth=399, LinkBandwidth=270
Over subscription and can't display".

 

I tried option 8 and the DPCD register values obtained for all 3 resolutions are below,

 

LINK_BW_SET (0x00100) status in DPCD = 14
LANE_COUNT_SET (0x00101) status in DPCD = 4
LANE0_1_STATUS (0x00202) in DPCD = 77
LANE2_3_STATUS (0x00203) in DPCD = 77

SYMBOL_ERROR_COUNT_LANE_0 (0x00210 and 0x00211) Status = 0A3
SYMBOL_ERROR_COUNT_LANE_1 (0x00212 and 0x00213) Status = 09
SYMBOL_ERROR_COUNT_LANE_2 (0x00214 and 0x00215) Status = 08
SYMBOL_ERROR_COUNT_LANE_3 (0x00216 and 0x00217) Status = 09

Selected Resolution = 3840x2160@60Hz
Selected BPC = 8

-------------------------------------------------------------------------------------------------------
LINK_BW_SET (0x00100) status in DPCD = 14
LANE_COUNT_SET (0x00101) status in DPCD = 4
LANE0_1_STATUS (0x00202) in DPCD = 77
LANE2_3_STATUS (0x00203) in DPCD = 77

SYMBOL_ERROR_COUNT_LANE_0 (0x00210 and 0x00211) Status = 088
SYMBOL_ERROR_COUNT_LANE_1 (0x00212 and 0x00213) Status = 0A
SYMBOL_ERROR_COUNT_LANE_2 (0x00214 and 0x00215) Status = 07
SYMBOL_ERROR_COUNT_LANE_3 (0x00216 and 0x00217) Status = 07

Selected Resolution = 3840x2160@60Hz (RB)
Selected BPC = 8

-------------------------------------------------------------------------------------------------------------
LINK_BW_SET (0x00100) status in DPCD = 14
LANE_COUNT_SET (0x00101) status in DPCD = 4
LANE0_1_STATUS (0x00202) in DPCD = 77
LANE2_3_STATUS (0x00203) in DPCD = 77

SYMBOL_ERROR_COUNT_LANE_0 (0x00210 and 0x00211) Status = 031
SYMBOL_ERROR_COUNT_LANE_1 (0x00212 and 0x00213) Status = 07
SYMBOL_ERROR_COUNT_LANE_2 (0x00214 and 0x00215) Status = 0A
SYMBOL_ERROR_COUNT_LANE_3 (0x00216 and 0x00217) Status = 0A

Selected Resolution = 3840x2160@30Hz
Selected BPC = 8

 

 

Out of these only 3840x2160@30Hz is working fine. How can I make 3840x2160@60Hz work?

Please let me know your inputs

 

Regards,

Vinay 

 

 

 

 

Vinay Shenoy
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Re: Display Port TX Design requirements

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Hi @vinay_shenoy

 

Could you tell me the followings ?

 

- DP Cable length

- DP Cable capacity

=> Is your DP cable an authenticated for 4K ?

- Can you prepare and add a common mode choke coil on DP cable ?

 

Your result is too wrong. It seems signal integrity issue or noise issue.

 

Best regards,

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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

Can you share what monitor you are using?

 

Can you try with a GPU to display 4K@60 RGB (and share a picture of the resolution showed in the monitor menu) and the GPU configuration?

I am not sure you monitor is able to support 4K60 RGB (it might support 4k@60 YCbCr422)

 

Regards,


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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

Do you have any updates on this? Were you able to have 4K@60 working?

 

Regards,


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Re: Display Port TX Design requirements

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Hi @florentw,

I tried modifying this example design and used a Xilinx Test Pattern generator instead of custom AV Generator and CRC helper core. Facing some issues with the display being not seen at monitor and was completely involved in debugging it.

 

Is it compulsory to have pixel per clock to be set to 4 for DP TX designs? I see the Video PHY automatically takes PPC as 4. My intention is to make it work with 2 PPC.
I should be able to make it work without helper cores. What do you think?


I didn't get enough time further debug DP UHD @60fps issues with example design. Maybe I will share you the Monitor details.

Regards,
Vinay

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Re: Display Port TX Design requirements

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HI @vinay_shenoy,

 

If you are doing 4K (no 8K) then you might be able to use 2ppc (it should be ok for timing). The configuration is do on the fly in the DP core

 

The DP IP had a different AXI4-Stream mapping than other video IP, refer to table 2-1 pg299. So you might need a specific IP to do the remapping. This will be changed in 2018.3 (the IP will follow UG934 as other video IPs)

 

Regards,


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Re: Display Port TX Design requirements

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HI @vinay_shenoy,

 

Do you have any updates on this? Were you able to make any progress?

 

Thanks and Regards,


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Re: Display Port TX Design requirements

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Hi @florentw

 

Thank you for following up. I appreciate your support.

 

I've tried checking with Xilinx pattern generator as well. In this case too, I was able to see display max. at UHD @30fps.

 

FYI, In my design I've got DP TX Subsystem v2.1 which as per PG299 follows DisplayPort standard 1.2a.

Also, I have checked the Xilinx DP TX only example design by importing both xdptxss_zcu102_dp14_tx and xdptxss_zcu102_tx application codes into sdk. Still, not able to work at UHD @60fps.

 

Is it possible for you to confirm the working of  Xilinx DP example design with UHD @60fps at your end?

 

Best Regards,

Vinay

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Re: Display Port TX Design requirements

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Hi @vinay_shenoy,

 

I confirm that I am able to do 4K@60 (with reduce blanking) with the DP1.2 SS IP. I already tested with KC705, KCU105 and ZCU102.

 

I am also able to do 4K@60 with the DP1.4 IP on ZCU102 and KCU105.

 

This is all with a 4K monitor DELL 2415Q.

 

Regards,


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Re: Display Port TX Design requirements

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Hi @florentw,

I'm using LG HDMI TV as sink - LG 40UF670T (http://www.fullspecs.net/lg/led-tv/40uf670t-specifications) .

I'm using a DP to HDMI converter (Adapter) to connect to this HDMI Monitor. I can guarantee that the DP to HDMI adapter supports UHD @60fps.

Regards,
Vinay
Vinay Shenoy
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