09-26-2019 10:34 PM
Hi i have generated display port ip example from Vivado v2019.1 ,compiled succesfully but in elaboration i am facing below error
"-- Loading module dp_ss_wrapper
-- Loading module unisims_ver.IOBUF
** Error: ../../../../dp_tx_subsystem_0_ex.srcs/sources_1/bd/dp_ss/hdl/dp_ss_wrapper.v(223): Module 'dp_ss' is not defined.
-- Loading module glbl
09-27-2019 02:08 AM
Kindly note that simulation for the Displayport TX Subsystem is not supported.
09-27-2019 02:41 AM
Hi Florent ,
I am not only doing simulation for the Displayport TX Subsystem .Please find the complete example of Block design.But compilation done successfuly during elaboration giving the Error.
09-27-2019 02:57 AM
Can you share the synthesis log?
10-01-2019 12:18 AM
I am confused. You said that you were getting errors. But looking at your log file, the simulation completes with no error:
335 Infos, 116 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully
Coud you clarify what error you are getting (outside simulation)?
10-01-2019 12:23 AM
Hi Florentw ,
I am doing simulation in questa sim .compilation is error free only during elaboration it is giving error .can you help me in resolving this .
10-01-2019 12:40 AM - edited 10-01-2019 12:41 AM
As mentioned in my first reply, simulation is not supported with the Displayport Subsystem IPs.Thus, no, I cannot help you with this as I do not have any working test bench and I am not even sure this will work.
You might want to avoid doing simulation with the Displayport Subsystems IPs