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3,611 Views
Registered: ‎08-06-2012

Display port v7.0 RX symbol lock issue

 

Hi Everyone,

 

    I am using the Display port IP v7.0 in my design with Zynq SOC. By using this I can validated the TX functionality of the IP with Display port capable DELL monitor(E1916H).  But while validating the RX functionality am getting symbol lock status failed during the Training pattern.

 

  During training pattern am getting CR done staus, EQ done status, Inter alignment status success. but symbol lock only failed. If anyone help on this it is very useful.

 

NOTE : My setup is one board with validated TX functionality as the TX source and another board have th RX core IP and trying the Training pattern. 

 

Thanks With Regards,

Venkatesh Babu.N

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13 Replies
Moderator
Moderator
3,593 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @venkateshbabuece,

 

First thing I might say is that the DisplayPort Logicore IP v7.0 is a discontinued IP. You should use the DP subsystems instead

 

Then I have some questions:

Are you using a Xilinx board?

 

Do you have a DP159? The Xilinx displayport IP expects you to use a DP159 retimer.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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3,531 Views
Registered: ‎08-06-2012

Re: Display port v7.0 RX symbol lock issue

 

Hi @florentw

 

       Since when we started this project, we did not have access to DP Subsystem IPs due to which we started with Standalone DP IP V7.0 and currently we are on strict deadline. Also we validated the TX functionality on this IP itself. So there is no enough time for us to completely change the block design and restructure the software configurations required for the DP Subsystems. I request you to kindly support on this IP for this time alone.

 

      As per our knowledge display port Subsystem using the display port V 7.0 Ip core. We would like to know if any particular update on the RX Display port IP core because without giving any configuration we are getting Symbol locked error count valid on the register(0x448 & 0x44C).   

 

Find answer for your queries below,

Then I have some questions:

Are you using a Xilinx board?   --- No (We are using our custom board refer the document attached for the setup information).

 

Do you have a DP159? The Xilinx displayport IP expects you to use a DP159 retimer.?

  --- Yes We have DP159 on our board.

 

   Kindly help on this we are struggling on symbol lock error only.

 

Thanks With Regards,

Venkatesh Babu.N

 

   

 

   

 

 

 

 

 

  

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Moderator
Moderator
3,513 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @venkateshbabuece,

 

Which device exactly are you using? And what vivado tool?

 

You are not using the clock provided by the DP159 while the IP is expecting it... I am not sure if you configuration can work...

This is important because the DP159 needs to tell you when the clock is locked.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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3,508 Views
Registered: ‎08-06-2012

Re: Display port v7.0 RX symbol lock issue

Hello @florentw,

  Thank you for your quick response.

   Device we used: Zynq(7Z045-2FFG900i)

   Tool we used: Vivado Design Suite 2016.4

 

   We used DP159 as per given in PG064 datasheet exactly. We were not getting clock at that time as well as CR lock on RX core. We removed DP159 and supplied 135MHz link clock from external source instead of DP159 for debugging purpose and at that time we are getting Clock recovery, Channel equalization(202,203 RX dpcd registers) and inter-lane alignment(204 RX dpcd registers) but Symbol lock is not coming/setting. We are getting symbol lock error count on 4 lanes(210-217 DPCD reg). We are not sure what might be the issue, Is it mandatory to use DP159 in the DP RX design. Does symbol lock latches upon clock recieved from DP159 aux pins or it latches from the clock recovered from the main link during training pattern 1?.

 

Is it possible to have a private conversation? 

 

We approached TI also for the same, and you can refer that using the link given below.

 

https://e2e.ti.com/support/interface/digital_interface/f/130/t/609275

 

Thanks with regards

Venkatesh Babu.N

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Moderator
Moderator
3,497 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @venkateshbabuece,

 

Did you have a look to xapp1178? The reference design may help you to see if you are missing something in your code.

 

Does symbol lock latches upon clock recieved from DP159 aux pins or it latches from the clock recovered from the main link during training pattern 1?.

-> I must say that I don't know. I will try to find the information


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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3,492 Views
Registered: ‎08-06-2012

Re: Display port v7.0 RX symbol lock issue

Hi @florentw

 

     Yes. we are following the Xapp1178 Code, exactly we are doing, but even then after configuring the DP159 through the I2C as per XAPP1178 also not able to get the Clock from the DP159. that's y we decided to remove the DP159. After removing only we are getting some status except that Symbol lock done.

 

    if possible kindly send us the working I2C configuration details for DP159 retimer for getting the clock at Aux Channel pins. 

 

Thanks With Regards,

Venkatesh babu.N

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3,489 Views
Registered: ‎08-06-2012

Re: Display port v7.0 RX symbol lock issue

Small addition with this In PG064 page number 95 mentioned in note IIC clock should be 400khz or more. but we are using 100Khz, But reading and writing to the IC happening. is it mandatory or 100Khz fine.
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Moderator
Moderator
3,425 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @venkateshbabuece,

 

if possible kindly send us the working I2C configuration details for DP159 retimer for getting the clock at Aux Channel pins. 

-> I don't have more than what is in the xapp

 

Small addition with this In PG064 page number 95 mentioned in note IIC clock should be 400khz or more. but we are using 100Khz, But reading and writing to the IC happening. is it mandatory or 100Khz fine.

-> Well I don't know. But you are taking a lot of risk. You might first follow the xapps because this are tested and validated solutions (which pass compliance). Then if you want to change stuffs you can starting from this. Lot of customer are doing it this way and have a successful experience.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer haidoph
Observer
2,966 Views
Registered: ‎02-24-2014

Re: Display port v7.0 RX symbol lock issue

hi,

    I now also encountered this problem, DP159 did not recovery the clock and pll unlocked。How did you solve it?

    

   thanks!

 

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Moderator
Moderator
2,290 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @haidoph,

 

Are you using the xapp as reference?

 

Are you using a xilinx board?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer haidoph
Observer
2,287 Views
Registered: ‎02-24-2014

Re: Display port v7.0 RX symbol lock issue

Are you using the xapp as reference?
yes,xapp1178 and xapp1271,Initialize DP159 according to XAPP,but DP159 PLL unlocked.
Are you using a xilinx board?
No (We are using our custom board
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Observer haidoph
Observer
2,227 Views
Registered: ‎02-24-2014

Re: Display port v7.0 RX symbol lock issue

hi,

Inrevium Kintex-7 FPGA ACDC1.0 base board (TB-7K-325T-IMG) +  TB-FMCH-DP3.1   

Can I use xapp1271 or xapp1178 directly?

because I do not have KC705 board。

 

thanks

 

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Moderator
Moderator
2,224 Views
Registered: ‎11-09-2015

Re: Display port v7.0 RX symbol lock issue

Hi @haidoph,

 

Inrevium Kintex-7 FPGA ACDC1.0 base board (TB-7K-325T-IMG) +  TB-FMCH-DP3.1   

Can I use xapp1271 or xapp1178 directly?

You will need probably need to make few changes on the HW (FPGA pins going to the FMC connector, maybe the UART + SPI also) but the application should be the same.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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