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Explorer
Explorer
1,001 Views
Registered: ‎05-03-2018

DisplayPort RX Subsystem v2.1 PG233

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Dear All,
About the DisplayPort RX Subsystem v2.1 PG233 page 59:

 

"RECOMMENDED: The Xilinx MMCM is not accurate enough to be used to regenerate the necessary clock
for non-frame buffer design. You need to use an external PLL that meets the requirements of the
DisplayPort Standard. See section 2.2.3 of the DisplayPort Standard v1.2a [Ref 9] for more details."

 

Can I have some more Infos about the external PLL ?
Because one of my customer want to use the external PLL but there are no specs.

 

Thanks in advance.

Best regards,

Andrea

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1 Solution

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Moderator
Moderator
945 Views
Registered: ‎11-09-2015

Re: DisplayPort RX Subsystem v2.1 PG233

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Hi @andreac_avnet,

 

As mentioned in the Product Guide, the XIlinx implemented solution is the solution with the frame buffer. The only guidance we can provide is to follow the displayport spec for the clock. We do not have a specific reference for a PLL clock.

 

Apart form that, the 3 possible solutions look correct.

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
5 Replies
Scholar watari
Scholar
974 Views
Registered: ‎06-16-2013

Re: DisplayPort RX Subsystem v2.1 PG233

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Hi @andreac_avnet

 

I'm not sure. But in this case, a design without frame buffer requests strictly native video clock.

Because of frame buffer works as cushioning for different clock frequency.

However, there is not in non-frame buffer design.

 

> Can I have some more Infos about the external PLL ?

 

So, it depends on your target resolution and FIFO length like called the line buffer.

 

Best regards,

 

Explorer
Explorer
952 Views
Registered: ‎05-03-2018

Re: DisplayPort RX Subsystem v2.1 PG233

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Dear @watari,

thanks for your reply.

 

Requested Resolution: we have to support the following two modes:

3200x1200 @120Hz sRGB

3200x1200 @60Hz sRGB 

 

Customer said: 

"About the FIFO length: we'd like to receive indications from Xilinx on this point.

What we have understood is that, considering the without-framebuffer mode, we could choose one of the 3 following implementations, to overcome

and manage the asynchronism between source &synch devices connected via DP:

1) use a high-precision 24-bit PLL 

2) use a lower precision (< 24-bit) PLL, together with a "small" FIFO with adaptive blanking to "absorb" and manage the source variations

3) do not use any PLL but put a big FIFO with adaptive blanking to "absorb" and manage the source variations

We 'd like to have instructions from Xilinx to correctly decide on component dimensions: in particular on scenario 1 we'd like to know which specific PLL with 24-bit precision we could use."

 

Best regards,
Andrea

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Moderator
Moderator
946 Views
Registered: ‎11-09-2015

Re: DisplayPort RX Subsystem v2.1 PG233

Jump to solution

Hi @andreac_avnet,

 

As mentioned in the Product Guide, the XIlinx implemented solution is the solution with the frame buffer. The only guidance we can provide is to follow the displayport spec for the clock. We do not have a specific reference for a PLL clock.

 

Apart form that, the 3 possible solutions look correct.

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Scholar watari
Scholar
934 Views
Registered: ‎06-16-2013

Re: DisplayPort RX Subsystem v2.1 PG233

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Hi @andreac_avnet

 

As @florentw already mentioned, I agree his suggestion.

 

If you only support the following resolutions. I think that it is easy. (Not need too big FIFO.)

 

- 3200x1200@120Hz

- 3200x1200@60Hz

 

Best regards,

 

Explorer
Explorer
917 Views
Registered: ‎05-03-2018

Re: DisplayPort RX Subsystem v2.1 PG233

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Dear @watari and @florentw,

Thanks both of you for the help.

 

Best regards,
Andrea

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