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Visitor billyyyy
Visitor
327 Views
Registered: ‎11-19-2019

DisplayPort Rx Subsystem Rx-only for zynq-7000

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Hi,
I am trying to implement a DisplayPort Rx-only system on a custom board with a 7045 soc. I used the rx-only example design for zcu102 as a start. I extracted the edid ip and frame_crc ip and then I connected all the things with the video phy controller and Dp rx subsystem the same as the example design does. In SDK, I modified the EDID and change the DP159 to gtrefclk0. I directly used my monitor's EDID and toke my PC's graphics card as the DP source, the resolution should be 1080p@60Hz. But the running results confused me and I can't even locate the problems. The axi4-stream output data are constant numbers and there is no begin or end pulse for a line. Some system reports are given below:
1. the video detected massage:
Video Detected --> Link Config: 5400x1, Frame: 1920x1080, MISC0: 0x20, Mvid=9011, Nvid=32768
[Video CRC] R/Cr: 0x0, G/Y: 0x0, B/Cb: 0x0


2. the MSA values:
XDP_RX_USER_FIFO_OVERFLOW (0x110) = 0x101
RX MSA registers:
Clocks, H Total (0x510): 2200
Clocks, V Total (0x524): 1125
HsyncPolarity (0x504): 0
VsyncPolarity (0x528): 0
HSync Width (0x508): 44
HSync Width (0x51C): 5
Horz Resolution (0x500): 1920
Verz Resolution (0x514): 1080
Horz Start (0x50C): 192
Verz Start (0x520): 41
Misc0 (0x528): 0x00000020
Misc1 (0x52C): 0x00000000
User Pixel Width (0x010): 1
M vid (0x530): 9011
N vid (0x534): 32768
M Aud (0x524): 0
N Aud (0x528): 0
VB-ID (0x538): 16

3.
DisplayPort RX Subsystem info:
DisplayPort Receiver(DPRX):Yes
IIC:Yes
Audio enabled:Yes
Max supported audio channels:2
Max supported bits per color:16
Supported color format:0
HDCP enabled:No
Max supported lane count:4
Max supported link rate:20
Multi-Stream Transport mode:No (SST)
Max number of supported streams:1
DP RX Subsystem is running in: SST with streams 1

4.
DP Link Status --->
LINK_BW_SET(0x400) status in DPCD = 0x14
LANE_COUNT_SET (0X404) status in DPCD = 0x1

LANEG_1_STATUS (0X43C) in DPCD = 0x7
LANE2_3_STATUS (0X440) in DPCD = 0x0

SYM_ERR_CNT01 (0x448) = 0x80008000
SYM_ERR_CNT23 (0x44C) = 0x80008000

PHY_STATUS (0x208) = 0x1000FF

5.
Video PHY Config/Status--->
RCS(0x10) = 0x8000015
PR (0x14) = 0x0
PLS(0x18) = 0xF
TXI (0x1C) = 0x8080808
TXIS(0x20) = 0×7070707
RXI(0×24) = 0x40404040
RXIS(0x28) = 0x3030303
GT DRP Addr (XVPHY_DRP_CPLL_FBDIV) = 0x5E, Val = 0x1080
GT DRP Addr (XVPHY_DRP_CPLL_REFCLK_DIV) = 0x5E, Val = 0x1080
GT DRP Addr (XVPHY_DRP_RXOUT_DIV) = 0x88, Val = 0x20
GT DRP Addr (XVPHY_DRP_TXOUT_DIV) = 0x88, Val = 0x20

6.
LOCK_STATUS : 64
TST_INT/Q : 0
BERT counter0[7:0] : 0
BERT counter0[11:8] : 0
BERT counter0[7:0] : 0
BERT counter0[11:8] : 0
BERT counter2[7:0] : 0
BERT counter2[11:8] : 0
BERT counter3[7:0] : 0
BERT counter3[11:8] : 0

Video PHY(8B10B):Error Counts [Lanel,Lane0] = [0,0]
Video PHY(8B10B):Error Counts [Lane3,Lane2] = [0,0]

for report #2, the fifo seems overflow, but I used a 200m clk which is surely enough. The MSA message came from the main link, does it means the training was done and the sink successfully received datas? But the VB-ID was wrong.
for report #4, it seems the all the plls are lock and no error.
for report #5, those DRP address have been modified to adapt the GTXE2, It seems all good.

But I still can't have any av output. Which part should I need to fix?

Thanks,
Bill

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Moderator
Moderator
126 Views
Registered: ‎11-09-2015

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Hi @billyyyy 

Are you checking the data before of after the video frame CRC? Please check before the frame CRC (i.e. directly after the Displayport Core) and let me know if you still have no data.

I beleive that in the RX only configuration the video CRC IP is not outputting any data


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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8 Replies
Moderator
Moderator
229 Views
Registered: ‎11-09-2015

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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HI @billyyyy 

I think you should start by focusing on the FIFO overflow. Make sure this is not the issue.

What happen if you read it multiple times with few second intervals? If the error stays this is likely to be the issue. Note that bit 0 will be cleared after the read, so a second read should not show the error.

If the FIFO overflow error reamins, could you give some details about the downstream IP? Are you using a Video frame buffer or VDMA? Are you sure this is not applying some back pressure?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
198 Views
Registered: ‎06-16-2013

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Hi @billyyyy 

 

What kind of DP source are you using ?

Also, do you implement DP159 as DP retimer on PCB ?

 

Best regards,

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Visitor billyyyy
Visitor
159 Views
Registered: ‎11-19-2019

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Thanks for reply! A second read on 0x110 is 0, the fifo overflow indicator is cleared. Repeat the read will have the same results. The only downstream IP is a system ila.
But when I changed the mtrefclk to other ports where even don't have any clock for input, I still got the same result as I posted....
The custom board I am using was verified, a dp rx design was implemented with the displayport 7.0 IP, which was already obsoleted.
One thing about dp159 made me confused. When dp159 works on x-mode, its i2c clock should be 400k or higher. But in the documents of dp159 and dp rx IP, the register 0x09 is set to 0x36, while in the example design of dp rx it is set to 0x37. In both cases I can read back what I have written but the problem still exist.

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Visitor billyyyy
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Registered: ‎11-19-2019

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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I am using an iMac and a PC, the source in PC is NVIDIA Quadro P5000.

The hardware I am working on was verified with another dp rx design which uses a displayport 7.0 IP, and that IP can't be used in the 2018 version Vivado.

When I use iMac for test, my design struggled a while on the training phase, like 10~30 seconds. But when test with NVIDIA Quadro P5000, the training will be done in just a few seconds.

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Moderator
Moderator
127 Views
Registered: ‎11-09-2015

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Hi @billyyyy 

Are you checking the data before of after the video frame CRC? Please check before the frame CRC (i.e. directly after the Displayport Core) and let me know if you still have no data.

I beleive that in the RX only configuration the video CRC IP is not outputting any data


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Scholar watari
Scholar
109 Views
Registered: ‎06-16-2013

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Hi @billyyyy 

 

Unfortunately, there are some compatibility issues in displayport 7.0 IP in your case.

So, I strongly recommend to upgrade displayport IP from it to latest version.

Would you consider it ?

 

Best regards,

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Visitor billyyyy
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Registered: ‎11-19-2019

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Yes, it is the problem. I received the data just after the DisplayPort core. Sorry for late reply, the computer I am working on is off line.

Visitor billyyyy
Visitor
61 Views
Registered: ‎11-19-2019

Re: DisplayPort Rx Subsystem Rx-only for zynq-7000

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Thanks a lot, actually this post is about upgrading the displayport IP....

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