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Observer dapaglia
Observer
1,086 Views
Registered: ‎10-02-2007

DisplayPort TX SubSystem AXI-Stream color format

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For the DisplayPort TX Subsystem IP, does the AXI-Stream input option support YUV422 mode?  There is no direct info on this, and the pixel mapping examples the document provides assume 3 component pixels.  Note that the documentation does indicate "dynamic support for YCbCr422" (among other modes), but I am wondering if that is more of a output conversion feature.

 

I am driving the DP TX core with a video TPG running in YUV422 mode, and while the timing is correct, the colors are way off, implying that I have some mismapping of the pixel data.  Could this be just a setup issue with the core, or a difference in mapping I'm not aware of, or does the core not support 422?

 

Thanks

--Dominic

 

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Observer dapaglia
Observer
1,564 Views
Registered: ‎10-02-2007

Re: DisplayPort TX SubSystem AXI-Stream color format

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Here's the solution in case others look this up.  Turns out the AXIS format is dependent upon the native format, and you need to pull bits of info from both sections to solve this.

 

Table 2-1 of PG199 shows that the AXIS input splits pixels into defined locations.  For YUV4:2:2, 10bit, start with the entry that shows 10 bits MAX_BPC and 10 bits Video BPC, 2 lanes.  This line shows that pixel 0 starts at bit 0 and pixel 1 starts at bit 30.  However, YUV4:2:2 shares components between pixels, so we need to understand how to split those components across two pixel locations.  Looking at the footnote of Table 2-2, we see that the native input splits YUV4:2:2 to be:

 

Pixel 0 = Cr Y0

Pixel 1 = Cb Y1

 

Thus, those components are mapped to the Pixel 0 and Pixel 1 portions as outlined in Table 2-1.  Back to Table 2-2, native format requires that the pixels are MSB justified, so the lower bits are unused.  Thus, the final AXIS formatting is.....

 

Y0 = [19:10]

Cr = [29:20]

Y1 = [49:40]

Cb = [59:50]

 

 

--Dominic

 

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Scholar austin
Scholar
1,074 Views
Registered: ‎02-27-2008

Re: DisplayPort TX SubSystem AXI-Stream color format

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d,

 

Page 922, ug1085

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer dapaglia
Observer
1,065 Views
Registered: ‎10-02-2007

Re: DisplayPort TX SubSystem AXI-Stream color format

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Thanks Austin.

 

UG1085 is for the Ultrascale+ DisplayPort that is part of the processor subsystem.  I'm using a DisplayPort TX Subsystem IP core (on a XCKU60, in case it matters).  Those functions listed on p922 don't exist on the IP core.  Is this document relevant to the IP core?

 

Thanks

--Dominic

 

 

 

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Scholar austin
Scholar
1,060 Views
Registered: ‎02-27-2008

Re: DisplayPort TX SubSystem AXI-Stream color format

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"The IP described by this document is designed to be compatible with DisplayPort Standard,
v1.1a and DisplayPort Standard, v1.2a. For silicon status, please check the Vivado® IP
catalog."

 

in pg064.

 

I suspect the DP IP core is just about moving data, and has no format/mode conversion features (per the earlt standards referenced).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Moderator
Moderator
1,001 Views
Registered: ‎11-09-2015

Re: DisplayPort TX SubSystem AXI-Stream color format

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Hi @dapaglia,

 

Yes you can do YUV422 with the AXI4 Stream interface of the DP TX SS.

 

The upper bit of the pixel should be unused in the case of YUV422.

 

One way to check is to add an ILA inside the DP SS (in the synthesized design) to check if the native interface (after the video bridge) corresponds to table 2-2 for the PG199

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer dapaglia
Observer
1,565 Views
Registered: ‎10-02-2007

Re: DisplayPort TX SubSystem AXI-Stream color format

Jump to solution

Here's the solution in case others look this up.  Turns out the AXIS format is dependent upon the native format, and you need to pull bits of info from both sections to solve this.

 

Table 2-1 of PG199 shows that the AXIS input splits pixels into defined locations.  For YUV4:2:2, 10bit, start with the entry that shows 10 bits MAX_BPC and 10 bits Video BPC, 2 lanes.  This line shows that pixel 0 starts at bit 0 and pixel 1 starts at bit 30.  However, YUV4:2:2 shares components between pixels, so we need to understand how to split those components across two pixel locations.  Looking at the footnote of Table 2-2, we see that the native input splits YUV4:2:2 to be:

 

Pixel 0 = Cr Y0

Pixel 1 = Cb Y1

 

Thus, those components are mapped to the Pixel 0 and Pixel 1 portions as outlined in Table 2-1.  Back to Table 2-2, native format requires that the pixels are MSB justified, so the lower bits are unused.  Thus, the final AXIS formatting is.....

 

Y0 = [19:10]

Cr = [29:20]

Y1 = [49:40]

Cb = [59:50]

 

 

--Dominic

 

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