UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
625 Views
Registered: ‎01-08-2018

DisplayPort TX Subsystem with Native Video input issue

Jump to solution

We seem to have run into the same issue raised in the post...

https://forums.xilinx.com/t5/Video/DisplayPort-TX-Subsystem-with-Native-Video-input/td-p/749638

 

Having changed the DisplayPort-Tx IP to Native mode we are no longer able to get video over the link, we have run through similar fault finding to the original poster.

Was this issue ever solved?

Has anyone shown the Native mode operation is working OK? (The design examples use streaming I/F).

 

The difference in our implementation to the original post are...

  • Vivado 2018.1
  • MST implementation : Pixel Mode Quad : MST Streams 2 : Bits Per color 10

Any help would be appreciated - thanks

0 Kudos
1 Solution

Accepted Solutions
Contributor
Contributor
538 Views
Registered: ‎01-08-2018

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

Hi @florentw

 

Thanks for your responses.

 

So we went back to the DisplayPort transmit design example for the ZCU102. Here exactly the same thing happened - it worked fine when in default SST streaming mode, but failed to work with MST (2 ports) Native Mode.

Going to the intermediate version : SST native mode (which I guess is what you have used) also worked.

 

After much effort we eventually worked out that the transceiver channels had been swapped around. Vivado had ignored the pinout constraints in the xdc file and swapped the pins around!

 

We were under the impression that the lines in the xdc file from the sample project should allow the correct pinout. This is what we had originally in the xdc...

# GT setting over write. Only for GTHE4. This xdc file has to be read at very last.
# This xdc file has to be read at very last. Current ZCU102 board has twisted GT pins assigned.
# Following constraints can over write the settng and can take user defined location instead.
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]

## DP TX pins
set_property PACKAGE_PIN G4 [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN G3 [get_ports {phy_txn_out[0]}]
set_property PACKAGE_PIN H6 [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN H5 [get_ports {phy_txn_out[1]}]
set_property PACKAGE_PIN F6 [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN F5 [get_ports {phy_txn_out[2]}]
set_property PACKAGE_PIN K6 [get_ports {phy_txp_out[3]}]
set_property PACKAGE_PIN K5 [get_ports {phy_txn_out[3]}]

 

We found that putting in blank pinout declarations 1st solved the problem...

# GT setting over write. Only for GTHE4. This xdc file has to be read at very last.
# This xdc file has to be read at very last. Current ZCU102 board has twisted GT pins assigned.
# Following constraints can over write the settng and can take user defined location instead.
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]

## DP TX pins
#clear the transceiver locations first!!
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[3]}]
#then set them where they are needed
set_property PACKAGE_PIN G4 [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN H6 [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN F6 [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN K6 [get_ports {phy_txp_out[3]}]
#set_property PACKAGE_PIN G3 [get_ports {phy_txn_out[0]}]
#set_property PACKAGE_PIN H5 [get_ports {phy_txn_out[1]}]
#set_property PACKAGE_PIN F5 [get_ports {phy_txn_out[2]}]
#set_property PACKAGE_PIN K5 [get_ports {phy_txn_out[3]}]

 

So we are not sure if this is a robust fix and also unsure why it broke when we went from Streaming mode to Native mode.

I also can't understand how Vivado can ignore pinout declarations and generate a bitstream - surely this is an error condition or at very least a critical warning? (I went back and looked at the messages and couldn't find even a warning message to indicate that pinouts had been swapped).

 

So we are back up and running thanks, hopefully it will remain working.

 

Best regards

John

 

0 Kudos
6 Replies
Moderator
Moderator
589 Views
Registered: ‎11-09-2015

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

HI @johnhd,

 

First I would recommend to use the AXI4-Stream interface as all the Xilinx Video IPs are using this interface. This is a good way to simplify development and only connects blocks together.

 

Then I have never used the Native Interface with MST but I have done it using SST and it is working for me. You might also want to start with SST and make sure you can get it to work.

 

You can check inside the DP subsystem IP. You will see how it is connected. The main core is using the native interface.

 

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
545 Views
Registered: ‎11-09-2015

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

Hi @johnhd,

 

Did you make any progress on this? Did you try to test with SST first?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Contributor
Contributor
539 Views
Registered: ‎01-08-2018

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

Hi @florentw

 

Thanks for your responses.

 

So we went back to the DisplayPort transmit design example for the ZCU102. Here exactly the same thing happened - it worked fine when in default SST streaming mode, but failed to work with MST (2 ports) Native Mode.

Going to the intermediate version : SST native mode (which I guess is what you have used) also worked.

 

After much effort we eventually worked out that the transceiver channels had been swapped around. Vivado had ignored the pinout constraints in the xdc file and swapped the pins around!

 

We were under the impression that the lines in the xdc file from the sample project should allow the correct pinout. This is what we had originally in the xdc...

# GT setting over write. Only for GTHE4. This xdc file has to be read at very last.
# This xdc file has to be read at very last. Current ZCU102 board has twisted GT pins assigned.
# Following constraints can over write the settng and can take user defined location instead.
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]

## DP TX pins
set_property PACKAGE_PIN G4 [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN G3 [get_ports {phy_txn_out[0]}]
set_property PACKAGE_PIN H6 [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN H5 [get_ports {phy_txn_out[1]}]
set_property PACKAGE_PIN F6 [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN F5 [get_ports {phy_txn_out[2]}]
set_property PACKAGE_PIN K6 [get_ports {phy_txp_out[3]}]
set_property PACKAGE_PIN K5 [get_ports {phy_txn_out[3]}]

 

We found that putting in blank pinout declarations 1st solved the problem...

# GT setting over write. Only for GTHE4. This xdc file has to be read at very last.
# This xdc file has to be read at very last. Current ZCU102 board has twisted GT pins assigned.
# Following constraints can over write the settng and can take user defined location instead.
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]

## DP TX pins
#clear the transceiver locations first!!
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN {} [get_ports {phy_txp_out[3]}]
#then set them where they are needed
set_property PACKAGE_PIN G4 [get_ports {phy_txp_out[0]}]
set_property PACKAGE_PIN H6 [get_ports {phy_txp_out[1]}]
set_property PACKAGE_PIN F6 [get_ports {phy_txp_out[2]}]
set_property PACKAGE_PIN K6 [get_ports {phy_txp_out[3]}]
#set_property PACKAGE_PIN G3 [get_ports {phy_txn_out[0]}]
#set_property PACKAGE_PIN H5 [get_ports {phy_txn_out[1]}]
#set_property PACKAGE_PIN F5 [get_ports {phy_txn_out[2]}]
#set_property PACKAGE_PIN K5 [get_ports {phy_txn_out[3]}]

 

So we are not sure if this is a robust fix and also unsure why it broke when we went from Streaming mode to Native mode.

I also can't understand how Vivado can ignore pinout declarations and generate a bitstream - surely this is an error condition or at very least a critical warning? (I went back and looked at the messages and couldn't find even a warning message to indicate that pinouts had been swapped).

 

So we are back up and running thanks, hopefully it will remain working.

 

Best regards

John

 

0 Kudos
Moderator
Moderator
534 Views
Registered: ‎11-09-2015

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

HI John,

 

Good to know that it is working back for you.

 

Vivado does not really ignore the pinout. It get the bank you are trying to select and place the pin in an aligned way (this is coming from constraints from the video phy).

 

The solution to unset the location is also what is used in the xdc for the example design on ZCU102

 

# GT setting over write. This xdc file has to be read at very last.
#set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
#set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
#set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
#set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Contributor
Contributor
434 Views
Registered: ‎01-08-2018

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

I see my earlier post has been accepted as a solution...

Personally I wouldn't call it a solution, I would call it a workaround.

The solution would be a fix in Vivado where the constraints set by the user are followed, if for whatever reason Vivado can't achieve the constraints (in this case the pinouts) then it should cause an error - just ignoring the pinouts is in my opinion unacceptable and leads to a huge amount of wasted time and a design that doesn't work.

0 Kudos
Moderator
Moderator
417 Views
Registered: ‎11-09-2015

Re: DisplayPort TX Subsystem with Native Video input issue

Jump to solution

HI @johnhd,

 

Sorry. We were not getting any reply from you, so we assumed it was clear for you.

 

I previously discussed with development related to the same issue on ZCU102. The answer was that the issue is more on the board layout than with the constraint as we expect the lanes to be correctly aligned as the GT.

 

But this should be documented, I will ask to have this in the Video Phy documentation.

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos