02-17-2017 07:38 AM - edited 02-17-2017 07:43 AM
I have an Artix-7 design that is using the DP TX SS 2.0 IP core, along with a xilinx-provided pattern generator which I have all working with my display. The Xilinx pattern generator is from xapp1271 (dp_video_pat_gen_v1_0) and it works in AXI stream mode for the video data to the DP core. I am now trying to use my own pattern generator with native video interface. So, I switch the DP TX SS core to "Native" video input (instead of stream), but I get nothing at all on my display. Everything else seems to be okay as far as the signals (looking in the ILA at Hsync, Vsync, enable) and the link status via the AUX channel reports 0x77 0x77 for the 4 lanes (CR done, EQ done, and all locked) but yet...nothing on the display. Is there something within the DP Core that I can probe for status with the ILA to see what's happening in this mode? Also, I am essentially using the software driver from xapp1271 and setting up the DP core, PHY, and AUX link using that software running on MicroBlaze.
Also I should note that even though I have chosen Single pixel mode, there are still 2 48-bit pixel inputs to the core (see attached pic), indicating that the setting is not working. So I have tried reducing the number of columns in half in case it is really running in dual mode, just as a test, but still nothing...
Thanks for any help!
02-17-2017 08:06 AM
What I advise you to try:
-> Use the pattern generator from the xapp with an AXI4-stream to video Out IP or you pattern generator with a video in to AXI4-stream and see if the result is the same.
About the configuration of the IP, which vivado version are you using? I am using 2016.4 and I can't see the same behavior:
02-17-2017 08:26 AM
Thank you for the reply. I am using Vivado 2016.1. There must be a bug with it. Nonetheless, I have tried to send it half as many columns(1920), and the full number(3840) - neither work.
I have tried my pattern gen with the "Video In to AXI4-Stream" IP (with DP set to stream mode) and had no luck. There were many signals that I didn't know what to do with though - it may be worth trying again. I could first try to convert the working pattern generator to native and try that?
02-17-2017 08:55 AM
It seems to convert the xapp pattern gen to native has lots of options for which I don't know what to do. See below, what do I do with the vtiming_in interface? Also the vid_io_out_ce? On the output side, the vid_io_out will not let me make a connection to the DP TX SS (wrong type). Also since there is no documentation on the xapp pattern gen, how do I match the pixels per clock, etc.? I am assuming it is 4 pixels per clock since the tdata scales to 95:0. But then the output side is 95:0 and the DP TX SS wants 47:0.
02-19-2017 11:55 PM
For the timing in, I would use a Video Timing controller. Then for the vid_io_out_ce you can leave it or put a constant 1.
On the output side, you can connect each signal under the interface. The size of the Dp inputs depends on your configuration.
02-20-2017 06:05 AM
Thanks for the reply...
Since I really want to run the DP core in native mode, this test is just to get the Xilinx xapp pattern generator to work by converting from streaming to native mode, but what does that prove? Are you thinking that maybe there's an issue with native mode on the core? To do this test that you suggest, when I instantiate the Video Timing Controller, there are options for Detection/Generation, am I correct to say that I don't need the AXI4-Lite interface, and I don't need to enable Detection?
02-20-2017 06:35 AM
I don't think there is an issue with the core in native mode but we never know. It is also to help you to compare what could miss in your design.
Yes, you need only generation in the VTC
02-20-2017 07:04 AM
Upon closer look at the auto-generated portion of the DP TX SS - I find this block diagram (this is what the tool auto-generates under the hood for the DP TX SS, it is not made by me). Note that there is already an AXI to native Bridge (which takes the xilinx streaming video Input and converts to native), a VTC is there, and then the DisplayPort core is always set to Native mode (there is no other option). If I probe the native video signals right at the input to the DP core, and I replicate them precisely with my own pattern generator, and with the DP core in native mode, it should work the same.
One confusing thing is if I double click the DP core, to look at how it is configured, there is no option for Native or Stream - maybe that's because it's auto-generated a certain way? The 2nd pic below here shows the options inside the DP core (within the auto-generated portion)
02-20-2017 08:42 AM
The displayport subsystem is a BD which includes the DisplayPort Logicore IP v7.0.
The DP Logicore V7.0 IP should not have the AXI interface. I guess that the selection of the native/axi interface in the DP SS IP will addor not the video bridge in the sub-BD of the Displayport subsystem.
02-20-2017 01:44 PM
I had a chance to compare all the DP register values (dumped from SDK memory window) between the working streaming mode one, and the non-working native mode. I noticed right away that address 0x000 (LINK_BW_SET) is 0x7 in the non-working one, and 0xA in the working one. From looking at the datasheet 0x7 is not even defined. However, the terminal output of the xapp1271 software says 'training ...... done!' which makes me think it worked fine as far as link negotiation. Do you know what the 0x7 means? Also, I have made the signals of my pattern generator match identically the ones on the native-side of the DP TX SS (set for stream), but still no luck.