08-11-2018 07:26 PM - edited 08-11-2018 07:31 PM
My custom board has Displayport Rx, the AUX channel is connected to 2.5V HR bank. As per VESA DP standard, AUX needs AC coupling and DC bias. The board uses 100nf for AC coupling, and 50 ohm resisters pullup to 1.25V at FPGA side.
When I probe the aux chanels, the waveform is strange, data packet's voltage amplitude is not the same. Does this related to incorrect terminations?
08-13-2018 03:42 AM
Yes it might be a wrong termintation. You might want to check the Inrevium DP FMC card for a compliant solution
08-13-2018 08:07 AM
08-17-2018 05:31 AM
The termination on the FMC card is as documented in the FMC card:
1MOhm pull pup -> capacitor -> 50 ohm register followed by a level shifter.
How are you doing the bidirectional? Is is internal to the FPGA or do you have an external buffer. Note that Xilinx mainly tested with external buffer (with unidirectional LVDS)
08-17-2018 07:34 AM
08-17-2018 07:45 AM
Could it be that your waveform analyzer is creating this floating waveform?
If GPU can access EDID, it might not be an issue.
08-22-2018 04:04 AM
08-22-2018 06:16 PM
10-24-2018 04:16 AM
01-02-2019 09:24 PM
Would you share version of DP Rx and a schema around DP ?
Also, would you turn off SSC at GPU, if possible ?
BTW, can you receive VGA video timing via DisplayPort ?
It means that I'd like to confirm whether it works fine under RBR (1.27Gbps) or not.