08-12-2019 10:40 PM
08-14-2019 09:33 AM
Please provide use some more details to understand your query clearly:
1. Your requirement and application details
2. Are you referring to any Xilinx example design? Please provide details.
08-15-2019 09:16 PM
I implemented video display port receiver subsystem example. In that they given Vid_EDID block and Video frame CRC block. I need that two blocks seperate files.
08-19-2019 02:58 AM
The Vid_EDID block and Video frame CRC block are what we call helper cores. They are used in the example design to demonstrate the behaviour of the Displayport core but they are not supported by Xilinx. Users are expected to write their own IPs for this blocs. This is why they are not part of the IP catalog and why there is not documnetation available.
You could potentially start from the example design to do your own project, but keep in mind that this is not fully supported.