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Observer prasanna_18
Observer
645 Views
Registered: ‎11-23-2018

Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

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 In our design we are using MIPI CSI-2 Receiver Subsystem v3.0  logiCore IP.

In that IP has MIPI D-PHY block.When I try customizing that block (we want to enable Enable HS and ESC Timeout counters/registers ) it doesn't reflect  in the block.

Not able to enable that interface.how can we enable that feature in our design?.

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1 Solution

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Xilinx Employee
Xilinx Employee
466 Views
Registered: ‎03-30-2016

Re: Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

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Hello @prasanna_18

As already mentioned by @bpatil, since you are using older version of MIPI CSI-2 Receiver Subsystem,
MIPI DPHY IP is set as a read-only IP and parameter modification cannot be easily done.
-- Manual RTL modification can be done, but I do not recommend this method.

Instead, we already added a new IP features in Vivado 2018.3.
Could you please download the latest Vivado and try the following step ?
0. Open MIPI CSI-2 Receiver Subsystem wizard GUI.
1. Check "D-PHY Register interface"
2. Check "Enable HS and ESC Timeout Counters/Registers"
3. Set the suitable HS and ESC Timeout value that fit your system

0110_XF_20183_MIPI_RX_CSI2_new_features.png

 


Hope this helps.

Thanks,
Leo

4 Replies
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Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎03-07-2018

Re: Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

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Hello @prasanna_18

You are not able to change any option of MIPI DPHY IP inside MIPI CSI-2 IP as it is read only.

MIPI CSI-2.png

 

 

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎03-30-2016

Re: Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

Jump to solution

Hello @prasanna_18

As already mentioned by @bpatil, since you are using older version of MIPI CSI-2 Receiver Subsystem,
MIPI DPHY IP is set as a read-only IP and parameter modification cannot be easily done.
-- Manual RTL modification can be done, but I do not recommend this method.

Instead, we already added a new IP features in Vivado 2018.3.
Could you please download the latest Vivado and try the following step ?
0. Open MIPI CSI-2 Receiver Subsystem wizard GUI.
1. Check "D-PHY Register interface"
2. Check "Enable HS and ESC Timeout Counters/Registers"
3. Set the suitable HS and ESC Timeout value that fit your system

0110_XF_20183_MIPI_RX_CSI2_new_features.png

 


Hope this helps.

Thanks,
Leo

Moderator
Moderator
337 Views
Registered: ‎11-09-2015

Re: Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

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HI @prasanna_18,

Do you have any updates on this? Were the replies from @karnanl and @bpatil enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer prasanna_18
Observer
233 Views
Registered: ‎11-23-2018

Re: Enable HS and ESC Timeout counters/registers in MIPI CSI-2 Receiver Subsystem v3.0

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Thanks for your patience and  support for this issue.

We will get back to you when we need your help.