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Explorer
Explorer
434 Views
Registered: ‎12-07-2018

External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hello, I am doing a PCB design that needs to generate 4 SDI streams that will be sent to a SDI monitor or frame grabber. This is my first experience with SDI and I am starting to look over the documentation for the TX IP Core. I want to configure the core as show in Figure 1.1:

UHD-SI_TX.jpg

 

 

I am trying to figure out how many external clocks the IP requires. Please tell me if the only external clock input is the "sdi_tx_clk" signal? I'm not sure about the "video_in_clk" so I'll need to keep reading the documentation. I am intefacing with a  LMH1297RTVT to create the SDI channel. 

http://www.ti.com/lit/ds/symlink/lmh1297.pdf

 

If anyone has some experience with this IP core can you please help me out.

Respectfully,

Joe

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Moderator
Moderator
272 Views
Registered: ‎11-09-2015

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hi @joe306 

No you also need 4*SMPTE UHD-SDI TX Subsystem to handle the data for each stream.

But you only need 1 UHD-SDI GT with these 4*UHD-SDI TX SS if all the tranceiver lanes are located in the same quad


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
8 Replies
Xilinx Employee
Xilinx Employee
403 Views
Registered: ‎03-30-2016

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hello @joe306 

Suggest you to generate the IP Example Design. Details is mentioned in PG289 Chapter 5.
sdi_tx_clk is coming from transceiver. ( The transceiver needs external REFCLK input tough )
You can use internal MMCM to generate video_in_clk.

https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf

Regards
Leo

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Xilinx Employee
Xilinx Employee
398 Views
Registered: ‎03-30-2016

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hello @joe306 

Attached the schematic from SDI example design.

Hope this helps.

Regards
Leo

Explorer
Explorer
345 Views
Registered: ‎12-07-2018

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Thanks Leo for responding to my message. How many SDI streams can the IP handle, is only one? I need to interface with 4 SDI cameras.

Last, what is the difference between the SMPTE UHD-SDI TX Subsystem v2.0 and the UHD-GT IP? 

It looks like the UHD-GT IP can support 4 streams. 

 

Thanks,

Joe

Xilinx Employee
Xilinx Employee
306 Views
Registered: ‎03-30-2016

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Yes. 4 streams are supported

 

Regards
Leo

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Moderator
Moderator
297 Views
Registered: ‎11-09-2015

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hi @joe306 

The UHD-SDI GT is controlling the PHY interface, i.e. the GTs.

It needs to be used with the UHD-SDI Transmitter subsystems which is controlling the SDI data layer.

Each UHD-SDI TX SS is responsible for one stream but you can use the same UHD-SDI GT with 4 UHD-SDI TX SS IPs if you need to have 4 streams in the same quad.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
275 Views
Registered: ‎12-07-2018

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hello, sorry to be so slow here to catch on, but If I drop in a UHD-SDI GT in my design is that all I need to hand 4-TX only SDI Streams?

 

Thank you very much,

Joe

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Moderator
Moderator
273 Views
Registered: ‎11-09-2015

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Hi @joe306 

No you also need 4*SMPTE UHD-SDI TX Subsystem to handle the data for each stream.

But you only need 1 UHD-SDI GT with these 4*UHD-SDI TX SS if all the tranceiver lanes are located in the same quad


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
269 Views
Registered: ‎12-07-2018

Re: External Reference Clock for SMPTE UHD-SDI TX Subsystem v.0

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Thank you very much for all your help. I'm slowly catching on. Thank's for not giving up on me and kicking me to the street. I appreciate all your comments. 

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