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5,139 Views
Registered: ‎04-02-2013

FFT and IFFT implementation in VERILOG using IP core

I'm using the FFT v7.1 core to perform both FFT and IFFT.

Features:

  • single channel
  • 8 points
  • floating point interface

in database it has given that by setting fwd_inv=1 FFT is performed and by setting fwd_inv=0 IFFT is performed.

but the thing is whether i set fwd_inv=0 or 1 am able to perform only one operation ie either FFT or IFFT.

 

to be specific in fixed point operation irrespective of the value assigned to fwd_inv (ie fwd_inv=0 or 1) only IFFT is happening... and in floating point operation irrespective of the value assigned to fwd_inv (ie fwd_inv=0 or 1) only FFT is happening..

can anyone please tell me the reason for this.. and can anyone suggest me how to perform FFT and IFFT using IP core in floating point/fixed point representation..

 

thank you

 

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Xilinx Employee
Xilinx Employee
5,101 Views
Registered: ‎08-02-2011

Re: FFT and IFFT implementation in VERILOG using IP core

Are you pulsing the fwd_inv_we signal when making changes?

www.xilinx.com
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5,056 Views
Registered: ‎06-16-2013

Re: FFT and IFFT implementation in VERILOG using IP core

`timescale 1ns / 1ps

 

module ifft_test;
always
begin
clk=1;
#10;
clk=0;
#10;
end

// Inputs
reg sclr;
reg ce;
reg start;
reg fwd_inv;
reg clk;
reg fwd_inv_we;
reg [31:0] xn_re;
reg [31:0] xn_im;

// Outputs
wire rfd;
wire dv;
wire done;
wire busy;
wire edone;
wire [31:0] xk_im;
wire [2:0] xn_index;
wire [31:0] xk_re;
wire [2:0] xk_index;

// Instantiate the Unit Under Test (UUT)
ifft uut (
.sclr(sclr),
.ce(ce),
.rfd(rfd),
.start(start),
.fwd_inv(fwd_inv),
.dv(dv),
.done(done),
.clk(clk),
.busy(busy),
.fwd_inv_we(fwd_inv_we),
.edone(edone),
.xn_re(xn_re),
.xk_im(xk_im),
.xn_index(xn_index),
.xk_re(xk_re),
.xn_im(xn_im),
.xk_index(xk_index)
);

initial begin
// Initialize Inputs
sclr = 0;
ce = 0;
start = 0;
fwd_inv = 0;
clk = 0;
fwd_inv_we = 0;
xn_re = 0;
xn_im = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
fwd_inv = 0;
fwd_inv_we =1;
ce = 1;
start = 1;
xn_re = 0; //5
xn_im = 0;
#20;
xn_re = 31'b00111111100000000000000000000000; //1
xn_im = 0;
#20;
xn_re = 31'b01000000101000000000000000000000; //5
xn_im = 0;
#20;

xn_re = 31'b01000000100000000000000000000000; //4
xn_im = 0;
#20;

xn_re = 31'b01000000110000000000000000000000; //6
xn_im = 0;
#20;

xn_re = 31'b01000000010000000000000000000000; //3
xn_im = 0;
#20;

xn_re = 31'b01000000101000000000000000000000; //5
xn_im = 0;
#20;

xn_re = 31'b01000000101000000000000000000000; //5
xn_im = 0;
#20;

xn_re = 31'b01000000101000000000000000000000; //5
xn_im = 0;
#20;
start=0;

xn_re = 0; //5
xn_im = 0;
#20;
xn_re = 0; //5
xn_im = 0;
#20;
xn_re = 0; //5
xn_im = 0;
#20;
xn_re = 0; //5
xn_im = 0;
#20;


end

endmodule

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