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Observer cbranson
Observer
9,040 Views
Registered: ‎09-12-2007

FIFO generation -- How to determine read delays

I have found myself frequently creating FIFOs.  Most are reasonably small so they have always seemed to output the requested data the clock cycle after data was requested.  Recently I was using a FIFO (64k deep x 32 bit) to interact with my design (this FIFO will not be left in the design when I generate the design).  I noticed it took ~5 clock cycles for the data to show up on the output port after it was requested. 
 
I need to have a signal that marks the start of the data.  To do this I just delay the same signal that requests the data.  This works fine if I know the delay but how do I calculate this delay?  My designs have to take on different sizes and thus I'd like to be able to vary my storage elements to minimize the resources they take up.  But if adding a larger or smaller FIFO changes the delay it will take a lot of work to re-time them every time. 
 
Could you tell me how to calculate these delays so I can know what FIFO sizes will give me the same output timing? 
 
I am also suggesting that the next version addresses this fact in the FIFO help file.  It does not and it seems like a very important parameter to know.
 
 
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Xilinx Employee
Xilinx Employee
9,037 Views
Registered: ‎08-07-2007

Re: FIFO generation -- How to determine read delays

I am not seeing a different in latency with the FIFO block whether I have a depth of 16 or a depth of 64k with a simple System Generator simulation.  With a constant 1 driving both the "we" and "re" ports the data presented on "din" always appears 3 clock cycles later on the "dout" port. 

Can you provide more detail about the scenario in which you're seeing the latency change?
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Observer cbranson
Observer
9,034 Views
Registered: ‎09-12-2007

Re: FIFO generation -- How to determine read delays

I am using System Generator 9.2i
 
It is configured for a 100MHz Virtex 2P in Verilog.
 
When using smaller FIFOs I'm only seeing a 1 clock cycle delay in WaveScope.   I see 3 when I increase the size of the FIFO. 
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Xilinx Employee
Xilinx Employee
9,032 Views
Registered: ‎08-07-2007

Re: FIFO generation -- How to determine read delays

I am still unable to reproduce the behavior you are describing. 

Please submit a webcase to Xilinx Tecnhical support to investigate this further.
http://support.xilinx.com/support/clearexpress/websupport.htm

Thanks
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Observer cbranson
Observer
9,029 Views
Registered: ‎09-12-2007

Re: FIFO generation -- How to determine read delays

I actually figured out my question but now it has created a new one:
 
I realized that the simulation started one of my data sets at t = 0 but started another at t = 1 thus I packed 0s into my FIFO (as the first entry).
 
Now that answers why the times are different but what it leaves me confused with is:
 
You said that you saw the delay as 3 clock cycles.  I only see it as 1.  Does WaveScope model this delay correctly? I'm worried I'm designing around a 1 cycle delay and it is really 3.
 
Thanks
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Xilinx Employee
Xilinx Employee
9,027 Views
Registered: ‎08-07-2007

Re: FIFO generation -- How to determine read delays

I found it took 3 clocks when the read and write enable are both held high for my inital data to make it's way to the output from an empty FIFO.  However for a FIFO that already has data in it the data appears at the output 1 cycle after the Read enable is asserted. 

the FIFO block utilizes the FIFO IP cores in Core Generator.  For details about the behavior you can reference the appropriate FIFO datasheet.  The core which is used is dependant on the target device as specified in the System Generator help for the FIFO block.
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