cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
209 Views
Registered: ‎08-13-2019

Facing issues with clocks for Vid_phy_controller and hdmi_rx_ss IP for zcu104 design

Jump to solution

Hi,

 

I'm design block diagram has flow below:

Vid_Phy_controller -> HDMI Rx subsytem - > video Frame buffer _wr -> Zcu 104

looking capture video using hdmi.

I has done IP interconnection with reference of HDMI reciever subsytem example : https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0083-video-hub.html

While implementation and write_bitstream facing the following error, let me how to fix. for more reference I has attached screenshoot of design.

Vivado 2019.1 version are using.

 

DRCPin Planning[DRC NSTD-1] Unspecified I/O Standard: 4 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: cable_detect_0, hpd_0, rx_tmds_clk_n_0, and rx_tmds_clk_p_0.
[DRC UCIO-1] Unconstrained Logical Port: 8 out of 9 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: cable_detect_0, hpd_0, mgtrefclk0_pad_n_in_0, mgtrefclk0_pad_p_in_0, CLK_IN_D_0_clk_p[0], CLK_IN_D_0_clk_n[0], rx_tmds_clk_n_0, and rx_tmds_clk_p_0.
ImplementationRoutingChip Level[DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/util_ds_buf_0/U0/IBUF_OUT[0].
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

Tags (2)
capture_error_design.png
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
122 Views
Registered: ‎04-09-2019

Re: Facing issues with clocks for Vid_phy_controller and hdmi_rx_ss IP for zcu104 design

Jump to solution

Hello @madan_1993 ,

It seems, specified I/o standards was not assigned to the I/O's of Your design. This is a known issue and it was already documented in our AR's. Could You please refer the AR#56354

I hope it helps to You.

With Regards,

Ashok

View solution in original post

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎04-09-2019

Re: Facing issues with clocks for Vid_phy_controller and hdmi_rx_ss IP for zcu104 design

Jump to solution

Hello @madan_1993 ,

It seems, specified I/o standards was not assigned to the I/O's of Your design. This is a known issue and it was already documented in our AR's. Could You please refer the AR#56354

I hope it helps to You.

With Regards,

Ashok

View solution in original post

0 Kudos