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Visitor
Visitor
3,337 Views
Registered: ‎06-14-2013

Failed to initialize ISIM engine

Hello,

 

I have a problem with running a simulation several times in a row under Xiling System Generator. The first time gives good results, but then after 2 or three simulations, according to the size of the design, I get this error message :

 

External Model firv6_3_CModel:firv6_3_cmodel threw std::exception:
ISim engine error: Failed to initialize ISIM engine.
Error occurred during "Simulation Initialization".

 

I saw a similar topic in this forum that was not solved, but it was posted 3 years ago, so maybe you have solved it since then even though I could not see it on your website. here is the board :

http://forums.xilinx.com/t5/DSP-Tools/Error-occurred-during-quot-Simulation-Initialization-quot/td-p/95814

 

So I guess there is a memory problem somewhere, can I do anything to really delete datas that were somehow stocked after the simulation ? (Clearing all the workspace does not function)

Or any other solution ?

 

I am using Matlab R2012b, windows XP 32-bits, ISE 14.4

 

Thanks

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Failed to initialize ISIM engine

You can clear the sysgen cache with this command:
>> xlCache('clearall')

Can you post the failing model? Try deleting the FIR compiler block. Does it still error? If not, then put it back in and try fiddling with the settings. Often times, these types of errors are due to a particular setting in a block and you may be able to work around it.
www.xilinx.com
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Visitor
Visitor
3,268 Views
Registered: ‎06-14-2013

Re: Failed to initialize ISIM engine

Thanks for your answer, even though I still have troubles.

 

When i am using the command "xlCache('clearall')", i get this kind of error message that is applied to a lot of files :

D:\Documents and Settings\T0143033\ApplicationData\Xilinx\Sysgen\nt\cache5\base\833a\e015a5eb0fe152000e482701d9a6\isim\fir_compiler_v6_3_control.dll.sim\netId.dat could not be removed.

I do not have all the admistrator rights on my computer, can it be a reason ?

 

Your remark about FIR compiler is really interesting because I am using them a lot, there are 6 of them (version 6.3) in my drawing for the moment , so maybe there is something wrong with my settings, so i give you the ones i am using :

  • single rate ones
  • one set of FIX 18/16 coefficients
  • one channel and path, maximum posible format
  • summetric structure, full precision
  • systolic_multiply_accumulate, area optimization, automatic memory ption and multi clumn supply, and 4 for pipe length
  • interface Aclken and Aresetn activated, driven by an impulse every 32 / 64 /128 ... samples (depending of which fir compiler) for the aclken, and a 1 to 0 signal for areset, step time at 2.

I just want a FIR operation, possibly reducing the resources needed, but i can change options if it can help the software to design, so are there some settings I should activate / unactivate among the ones I quoted ?

 

Unfortunately, I do not think I will be allowed to send you the failing model, for confidentiality reasons, but i will see if I can alter it so that it is not a problem.

 

Anyway, thanks for your answer !

I now think there may be a problem with the FIR compiler, unfortunately I have to use them...

 

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Visitor
Visitor
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Registered: ‎06-14-2013

Re: Failed to initialize ISIM engine

I tried to delete the previous post, but I could not find how.

 

I tried to isolate the block that could be a problem, as you suggested, and it appears that it was not the FIR compiler, but one of the black box I am using.

I tried without it, I could run the simulation 10 times in a row. With it, the "initialisation problem" comes after 2 simulations. If I keep only the fir compiler, I do not have troubles. Therefore thanks to you I probably found where there is a problem.

 

But I still cannot understand why there is a problem.

As I said, it is a black box coded in VHDL that has been designed by Thales C&S several years ago, so the problem could be in the code and in this case you could do nothing. However there still are 2 points that bother me :

  • I know for sure the black box has already functionned, at least in earlier version with matlab 2010b and Xilinx System Generator 12.4. Is there something I have to change or add in the vhdl code so that it is still compatible with matlab 2012b and XSG 14.4 ?
  • the troubles only come after several utilisations, so in a way the code has to be good because it can run at least once.

If you know how to fix it or have ideas about how to investigate it, I will be glad to know.

Thanks again for your help

 

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