UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
199 Views
Registered: ‎10-18-2017

Frame Buffer Read IP and 64-bit Addressing on PetaLinux UltraScale+

Jump to solution

I have been looking through the DMA API for PetaLinux with special attention toward UltraScale+ Platform. Because the Frame Buffer Read 2.1 IP PetaLinux API looks like a wrapper around the Linux DMA engine, it follows that similar hardware configurations that are required for DMA transactions betweeen the UltraScale+ and AXI DMA IP should be required for the Frame Buffer Read IP. Correct me if I am wrong. The most important of these issues is to allow for 64-bit addressing, the details of which are documented here. My understanding is that the upper 2 GB of RAM on ZCU102 (I am using ZCU104 which I am assuming has same DDR controller) is reserved for "high memory" or memory whose address translation extends beyond the 2^32 boundary associated with classical Linux systems on 32-bit processors like Cortex A-9 on Zynq-7000. Again correct me if I am wrong.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842169/PL+Masters

My issue is how to extend this to the FrameBuffer Read IP. I have configured Zynq UltraScale+ block to allow for high addressing, and have allowed for 64-bit address width in the FrameBuffer Read IP.

ipconfig2.png

For whatever reason, I am not able to map UltraScale+ S_AXI_HP0_FPD, HP0_DDR_HIGH into the address space in the "Address Editor" tab in Vivado. Why is this address space not showing up?

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
131 Views
Registered: ‎11-09-2015

Re: Frame Buffer Read IP and 64-bit Addressing on PetaLinux UltraScale+

Jump to solution

HI @johnfrye11 ,

I do not think the ZCU102 and ZCU104 are using the same DDR. You have more DDR addressable memory on the ZCU102.

A good way to confirm this for the ZCU104 is to go in the ZU+ configuration GUI, in DDR configuration, if you change the configuration for DRAM DDevice Capacity (per die) to 8192 MBits, you will see that you will be able to access the DDR_HIGH in the address editor (but of core this would not work in your HW).

Hope that helps,

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Moderator
Moderator
132 Views
Registered: ‎11-09-2015

Re: Frame Buffer Read IP and 64-bit Addressing on PetaLinux UltraScale+

Jump to solution

HI @johnfrye11 ,

I do not think the ZCU102 and ZCU104 are using the same DDR. You have more DDR addressable memory on the ZCU102.

A good way to confirm this for the ZCU104 is to go in the ZU+ configuration GUI, in DDR configuration, if you change the configuration for DRAM DDevice Capacity (per die) to 8192 MBits, you will see that you will be able to access the DDR_HIGH in the address editor (but of core this would not work in your HW).

Hope that helps,

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
96 Views
Registered: ‎11-09-2015

Re: Frame Buffer Read IP and 64-bit Addressing on PetaLinux UltraScale+

Jump to solution

Hi @johnfrye11 ,

Do you have any updates on this? Was my reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos