02-09-2018 06:35 AM
I am using a Zynq US+ 7EV. I have a pair of UHD-SDI rx/tx subsystems in Bank 226. They supposedly share REFCLKs and PLLs. They are configured for 3G, max. The design validates and synthesises OK. But when I implement, it fails in placer. Says the design requires 5 GT commons when the chip has only 4. Now, I have HDMI RX subsystems in banks 224 and 225, and PCIe in bank 227, so each of those banks is using its own common. That leaves 1 common cell for the SDIs in bank 226. Is there any chance the pair of UHD SDIs require more than 1 common? The error report does not tell me the offending IP. I doubt the other GTs in the other banks are needing more than 1 common per bank.
02-12-2018 03:51 AM
If I am not wrong, with the UHD-SDI subsystems, the GTs are outside the cores. So it might be up to the user to manage them.
How did you implement the GT part? Did you use the example design provided in vivado (ZCU106)? I will try to look at the implemented design for the exdes but I would expect that it is using only on GT common.
02-12-2018 06:01 AM
I have checked with the example design for the UHD-SDI Subsystems (can be generated from the UHD-SDI RX SS on ZCU106 with 2017.4). This design is using both UHD-SDI TX and RX and is using only one GT Common as per the search for GT common in the implemented design:
Thus, it is possible to use only one GT common for both TX and RX.
You might want to start with this example design.
02-13-2018 08:41 AM
@bmoore Please open Synthesized design, and then use Edit -> Find GTHE4_COMMON, and then click ok
Based on the Find result, you should be able to figure out in which hierarchy level, you have unexpected GT COMMON block.
Probably you need to do necessary modification in your design.
03-06-2018 03:37 AM - edited 03-06-2018 03:47 AM
If everything is clear for you on this subject, please kindly mark a reply as solution to close the topic. Else please reply to the thread.
Thanks and Regards,