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Observer bmoore
Observer
1,282 Views
Registered: ‎01-09-2018

Getting video into the Zynq VCU

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I have 2 AXI video streams. I want to compress them via H.264 in the VCU. The VCU pg252 does not show how video from the outside the IP is input to it. IS it via the S_AXI_HPCx_FPD ports on the Zynq? What other IP do I need to input the video? A VDMA? A video frame buff write?

 

Also I am using the video_in _to AXI4_stream IP to get video into the AXI stream. The ADV7181 video decoder chip I am using does not have H/V blanking signals, but the IP has blanking signal inputs. How should these be tied off if these signals are not available from the source? Also, for interlaced signals, the ADV7181 has a dual purpose DE/FIELD pin which outputs odd/even field for NTSC/PAL, but active video for VGA type sources. Can the IP make do without an active video signal for NTSC/PAL? Can it figure out from the VTC where blanking should be? Conversely can it figure out odd/even field info from the HS and VS signals alone, without a separate field ID pin?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Re: Getting video into the Zynq VCU

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The VCU is a memory based encoder that uses Semi-Planer format as described in the Source Frame Format section of PG252

 

Since your incoming video is in standard video format from the ADV7181, you are correct to use the Video In to AXI4-Stream bridge will convert to AXI4-Stream.  The Video In to AXI4-Stream uses the Video Timing Controller to detect the resolution of the incoming data.  The Video Timing Controller does need the Active Video Signal along with either the Blanking or Sync signals to detect the full timing.  You should be able to tie off the unused blanking inputs to ground.  Page 5 of PG043 lists the valid combinations needed in order to properly detect the timing.  You may need to work with Analog Devices to create a circuit to generate the necessary Data Valid in order to properly detect the incoming video resolution.

 

Next you will need to use the Video Frame Buffer Write to write your incoming AXI4-Stream data to memory.  You can do this through the S_AXI_HPCx_FPD ports.  You will need to make sure that you configure the Video Frame Buffer Write to write the data into DDR in the correct format.  You then use the Video Frame Buffer Read to read the data out of DDR after compression by the VCU.

 

Keep in mind that the VCU currently does not support interlaced video formats.  Per page 5 support for progressive encoding is supported for H.264 and H.265, while interlaced support for H.265 encoding is under development, but not yet ready.  If you incoming video is interlaced, then you will need to look at using the Video Processing Subsystem Deinterlacer function to convert to Progressive video before writing to memory with the Video Frame Buffer Write.

Chris
Video Design Hub | Embedded SW Support

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3 Replies
Moderator
Moderator
1,245 Views
Registered: ‎11-09-2015

Re: Getting video into the Zynq VCU

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Hi @bmoore,

 

You can connect the VCU directly to the zynq MPSoC (check the chapter 10 - Design Flow steps of the VCU PG252) or you can use the video frame buffer. It depends on your needs.

 

Also I am using the video_in _to AXI4_stream IP to get video into the AXI stream. The ADV7181 video decoder chip I am using does not have H/V blanking signals, but the IP has blanking signal inputs. How should these be tied off if these signals are not available from the source?

You should be able to connect only vblank and hblank and leave the other signals unconnected.

 

Can the IP make do without an active video signal for NTSC/PAL?

No I think you need the video active signal (at least for the vct)

 

Conversely can it figure out odd/even field info from the HS and VS signals alone, without a separate field ID pin?

No I think you need this signal.

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Xilinx Employee
Xilinx Employee
1,745 Views
Registered: ‎08-01-2007

Re: Getting video into the Zynq VCU

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The VCU is a memory based encoder that uses Semi-Planer format as described in the Source Frame Format section of PG252

 

Since your incoming video is in standard video format from the ADV7181, you are correct to use the Video In to AXI4-Stream bridge will convert to AXI4-Stream.  The Video In to AXI4-Stream uses the Video Timing Controller to detect the resolution of the incoming data.  The Video Timing Controller does need the Active Video Signal along with either the Blanking or Sync signals to detect the full timing.  You should be able to tie off the unused blanking inputs to ground.  Page 5 of PG043 lists the valid combinations needed in order to properly detect the timing.  You may need to work with Analog Devices to create a circuit to generate the necessary Data Valid in order to properly detect the incoming video resolution.

 

Next you will need to use the Video Frame Buffer Write to write your incoming AXI4-Stream data to memory.  You can do this through the S_AXI_HPCx_FPD ports.  You will need to make sure that you configure the Video Frame Buffer Write to write the data into DDR in the correct format.  You then use the Video Frame Buffer Read to read the data out of DDR after compression by the VCU.

 

Keep in mind that the VCU currently does not support interlaced video formats.  Per page 5 support for progressive encoding is supported for H.264 and H.265, while interlaced support for H.265 encoding is under development, but not yet ready.  If you incoming video is interlaced, then you will need to look at using the Video Processing Subsystem Deinterlacer function to convert to Progressive video before writing to memory with the Video Frame Buffer Write.

Chris
Video Design Hub | Embedded SW Support

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Observer bmoore
Observer
1,179 Views
Registered: ‎01-09-2018

Re: Getting video into the Zynq VCU

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Ok thanks, it answers the question.

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