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Observer rishubnagpal
Observer
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Registered: ‎04-19-2018

Guidance on designing a simple video processor

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Hi,

 

I'm having trouble grasping how exactly to design a video processing application using Xilinx IPs. My device is the Nexys 4 DDR (artix-7)

 

I have written a custom IP which takes in a 640x480 video from a camera and converts it into an AXI4-Stream. I wish to pass the video through a filter and output to VGA. My design is as follows:

 

Camera input to AXI-Stream -> Video Filter -> Frame buffer -> AXI - Stream to Video Out

 

 

Questions:

 

1) I'm not sure what to use for the framebuffer. I've read through the VDMA, FIFO Generator, Video Frame Buffer R/W IP guides but I don't know which would work the best in my case. If possible, I'd like to store the frame in block ram. In the past, I've used the Block memory generator IP to do a similar application, but that IP is not AXI compliant. What would be the best memory IP to use in this case? Would it make sense to use block ram? What would be the easiest approach to this?

 

2) Will I need a MicroBlaze processor to achieve this application? I am willing to learn but I have no experience with using a softcore processor

 

Thanks, any guidance or input would be very appreciated! 

 

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Explorer
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Registered: ‎07-18-2011

Re: Guidance on designing a simple video processor

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For a simple frame buffer, a VDMA will work fine.  You can configure it to drop or repeat frames as necessary to keep from overwriting the frame you are currently reading.

 

There is not enough block RAM in an Artix-7 to store an entire RGB frame of video.  Actually, in order to create a seamless flow with no image "tearing" you normally use three frames of memory for the VDMA.    You will need to add a MIG IP block to interface DDR3 to store the required three frames of video.

 

While it is possible to control VDMAs without a MicroBlaze, by using the AXI Traffic Generator IP to load the VDMA settings, it is easier to use the MicroBlaze, which will give you a lot more control/debug options.

 

Also, it is usually easiest to put your custom IP on the read side of the frame buffer if you can, because you can process the data at a different rate without having to remain locked to the input data flow from your camera, as you will on the write side, where you can only process data at the rate it comes in.

 

 

 

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Explorer
Explorer
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Registered: ‎07-18-2011

Re: Guidance on designing a simple video processor

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For a simple frame buffer, a VDMA will work fine.  You can configure it to drop or repeat frames as necessary to keep from overwriting the frame you are currently reading.

 

There is not enough block RAM in an Artix-7 to store an entire RGB frame of video.  Actually, in order to create a seamless flow with no image "tearing" you normally use three frames of memory for the VDMA.    You will need to add a MIG IP block to interface DDR3 to store the required three frames of video.

 

While it is possible to control VDMAs without a MicroBlaze, by using the AXI Traffic Generator IP to load the VDMA settings, it is easier to use the MicroBlaze, which will give you a lot more control/debug options.

 

Also, it is usually easiest to put your custom IP on the read side of the frame buffer if you can, because you can process the data at a different rate without having to remain locked to the input data flow from your camera, as you will on the write side, where you can only process data at the rate it comes in.

 

 

 

Observer rishubnagpal
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Registered: ‎04-19-2018

Re: Guidance on designing a simple video processor

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Thanks @reaiken

 

My device has enough block ram (4,860 Kbits) to store a 640x480 frame, and only has DDR2 memory. Would you still recommend to use VDMA?

 

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Registered: ‎07-18-2011

Re: Guidance on designing a simple video processor

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@rishubnagpal

 

A single 640x480 frame of 24-bit RGB data requires:  640 pixels * 480 lines * 8 bits/pixel * 3 RGB components = 7,372,800 bits  = 7200 kbits.  In order to do frame synchronization, you need 3 times this amount, in order to allow for the three frames of memory.  

Your XC7A100T device only has 4860 kbits = 4860*1024 = 4,976,640 bits available. 

 

Even if you are only doing 8-bit monochrome 640x480, you would still need 2,457,600 bits/1024 = 2400 kbits for each of the three frames required, which means you still don't have enough block ram to process the video frames.

 

So, yes, I still recommend VDMA, and you will need a MIG for your DDR2.

 

 

 

 

Observer rishubnagpal
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Registered: ‎04-19-2018

Re: Guidance on designing a simple video processor

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@reaiken

Is there a reason to recommend the VDMA IP vs the Frame Buffer R/W IP?
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Explorer
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Registered: ‎07-18-2011

Re: Guidance on designing a simple video processor

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@rishubnagpal

 

Yes, either one will work, but the VDMA IP is simpler to use because it will take care of the master/slave relationship between the input and output side VDMA for you, as opposed to having to monitor and control the read and write side in software to keep the reads and writes from overlapping in the middle of a frame, which will cause a "tear" in the image when a read frame contains a mix of old and new data. 

 

The VDMA will also automatically cycle through the 3 frame buffers for you.   The Video Frame Buffer Read and Write will require  software to monitor the interrupts at the end of a frame to reprogram the next buffer address as necessary.

 

You can set up a single VDMA IP instance as a combination read and write channel, configure the write side as master and read side as slave, and set it up for 3 frame buffers, and it will do what you want with no further control or monitoring.

 

If you read the product guide documentation for each IP, the differences and usage will be clear.

 

 

Observer rishubnagpal
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Registered: ‎04-19-2018

Re: Guidance on designing a simple video processor

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@reaiken Thanks for your help! 

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Explorer
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Registered: ‎07-18-2011

Re: Guidance on designing a simple video processor

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@rishubnagpal

 

You're welcome!

 

A bit of clarification - the VDMA IP will still require a small amount of software initialization to configure the 3 buffer start addresses and a few configuration registers for H size, H stride, and V size, but it won't require constant software monitoring of an interrupt at the end of every frame.   The user guide and IP examples will illustrate the steps you need to take to initialize the IP.  

 

 

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