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Adventurer
Adventurer
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Registered: ‎01-19-2018

HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hello,

I am implementing the kc705 HDMI Rx SS  design, it works good.
Now i have just added Video Processing SS for Color Space Conversion to YUV_442 from RGB, the probe shows all the stream are inactive.

How to analyze the system?

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @daram123,

 

I believe I understand. It sounds like the VPSS is not asserting TREADY on its input even though it is high from the HDMI on its output. 

 

This sounds like there may be an issue initializing the VPSS.

 

To move forward, please enable the driver to provide a log. This should report issues with the core.

Also, check to see that the cores clocks are connected properly and that the MMCM is locking.

From PG231 page 57:

2018-10-15 10_07_34-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

Regards,

Sam

 

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Xilinx Video Design Hub
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Moderator
Moderator
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Registered: ‎10-04-2017

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @daram123,

 

Do you have a debug (uart/jtag) output in your system? If so, are the drivers reporting any errors?

 

Also, for video debug of video streams, check for backpressure (tready low). If tready is low on any core, it is not ready to receive data and is putting backpressure into your system.

 

For more information on AXI-S for video, UG934:

see http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

-Sam

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Xilinx Video Design Hub
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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Video Processing Sub sytem receive tready from HDMI Tx.. Thereafter, th tready is not passing out of the VIdeo Processig SS.

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @daram123,

 

To confirm, are you saying that tready from the HDMI TX is never high? If so, there is an issue initializing your HDMI. This is most likely in your application code. 

 

Do you have a debug (uart/jtag) output form your system? Can you add this here?

 

-Sam

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Xilinx Video Design Hub
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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @samk tready from the HDMI TX is high, Only the Video Processing subsystem does not allow to pass the tready signal..

I hope i am clear.

Regards,
Prasanna Daram

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @daram123,

 

I believe I understand. It sounds like the VPSS is not asserting TREADY on its input even though it is high from the HDMI on its output. 

 

This sounds like there may be an issue initializing the VPSS.

 

To move forward, please enable the driver to provide a log. This should report issues with the core.

Also, check to see that the cores clocks are connected properly and that the MMCM is locking.

From PG231 page 57:

2018-10-15 10_07_34-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: HDMI 1.4/2.0 Receiver Subsystem Exdes 2018.2

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Hi @daram123,

 

Do you have any updates on this? Was the reply from @samk enoufh for you?

 

I guess this is now working as per https://forums.xilinx.com/t5/Video/HDMI2-0-exdes-Rx-Tx-Kc705/m-p/905161#M22415

 

Can you please kindly give your solution to the community and close the topic? This could probably help other users.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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