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Contributor
Contributor
709 Views
Registered: ‎12-02-2016

HDMI 1.4/2.0 Receiver Subsystem supported resoluation

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Hi,

    My board needs to receive video with resoluation of 5760*1200@60 from HDMI port。PG236 states that it can  support resolutions up to 4096*2160@60, I have already verified that. Howerver, the HDMI receiver subsystem cannot receiver or reconglize 5760*1200@60, though the max datarate is not excess maxium throughput.

Is that kind of resoluation supported by HDMI receiver subsystem?  if yes , how to deal with that.

thanks!
 

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Xilinx Employee
Xilinx Employee
635 Views
Registered: ‎08-02-2007

Re: HDMI 1.4/2.0 Receiver Subsystem supported resoluation

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Hi @xxhc417s

5760*1200@60 is not defined in the CEA-861-F spec, so you need to add custom timing information manually. Please refer to AR#68227 for more details on how to add custom resolution : https://www.xilinx.com/support/answers/68227.html

The other thing to check is if the link clock falls in the supported range of QPLL or CPLL.

- You can refer to Clocking Section (page 41-42) of https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf

and calculate the link clock frequency.

- Then you can refer to Table 3-3, Table 3-5,Table 3-6, Table 3-8, Table 3-10 of PG230 : https://www.xilinx.com/support/documentation/ip_documentation/vid_phy_controller/v2_2/pg230-vid-phy-controller.pdf

and try to figure out the supported range based on your device family type.

 

 

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
636 Views
Registered: ‎08-02-2007

Re: HDMI 1.4/2.0 Receiver Subsystem supported resoluation

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Hi @xxhc417s

5760*1200@60 is not defined in the CEA-861-F spec, so you need to add custom timing information manually. Please refer to AR#68227 for more details on how to add custom resolution : https://www.xilinx.com/support/answers/68227.html

The other thing to check is if the link clock falls in the supported range of QPLL or CPLL.

- You can refer to Clocking Section (page 41-42) of https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf

and calculate the link clock frequency.

- Then you can refer to Table 3-3, Table 3-5,Table 3-6, Table 3-8, Table 3-10 of PG230 : https://www.xilinx.com/support/documentation/ip_documentation/vid_phy_controller/v2_2/pg230-vid-phy-controller.pdf

and try to figure out the supported range based on your device family type.

 

 

 

 

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Contributor
Contributor
601 Views
Registered: ‎12-02-2016

Re: HDMI 1.4/2.0 Receiver Subsystem supported resoluation

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Hi, xud

Thanks, I have tried your methord, but  HDMI Receiver Subsystem still cannot recongnize that resoluation, information:
------------
HDMI RX timing
------------
No HDMI RX stream
Link quality
---------
Link quality channel 0 : bad (65535)
Link quality channel 1 : bad (65535)
Link quality channel 2 : bad (65535)

I have read EDID V1.4, however it states thats horizontal active piexls cannot exceeds 4096. So that means one just cannot use resoluation of 5760*1200? 

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Contributor
Contributor
579 Views
Registered: ‎12-02-2016

Re: HDMI 1.4/2.0 Receiver Subsystem supported resoluation

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I have received video with resoluation of 5760*1080  by using HDMI  Rx Subsystem directely. There is no need to set up custom resoluation.  5760 active lines is not supported by EDID, but HDMI diver doesn't check it, as AXI stream carrys only valid pixels. The following function depicts all:

int XV_HdmiRx_GetVideoTiming(XV_HdmiRx *InstancePtr)

 

 

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