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Adventurer
Adventurer
4,286 Views
Registered: ‎06-13-2012

HDMI 2.0 Tx_TMDS_CLK_p/n source

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Hi,

 

I'm designing an HDMI 2.0 application with xilinx IP, I'm reading the datasheet and the reference design XAPP1287.
It uses the inrevium board that has a clock mux on the HDMI Source side (Tx_TMDS_CLK). The mux input comes from one transceiver channel and from a LVDS source, I would like to understand why and when it uses the transceiver input and when the other input. I can figure out that's due to the transceiver high speed, it's to use a slower (LVDS) clock to support video formats under 720p50?

Thank you for your support

 

regards

 

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Xilinx Employee
Xilinx Employee
7,523 Views
Registered: ‎08-01-2007

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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The Video PHY Controller v2.0 does not support generating the TMDS Clock from the unused GTH in a quad.

The source for the Video PHY Controller is in clear text and you could modify it to use the Video PHY and the Driver to generate the clock with the unused GTH.  This flow is not officially supported, once you modify the code you are responsible for testing and verification.

Chris
Video Design Hub | Embedded SW Support

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Xilinx Employee
Xilinx Employee
4,210 Views
Registered: ‎08-02-2007

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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GT doesn’t support TMDS Level signals. The CLK_TX_LVDS is at 3.3 V level, MGTAVCC is 1.2V. External level shifter ASSPs are need to do TMDS Level shifting job. TI SN65DP159 (which can be seen on inrevium board and ZCU102) is fully tested with HDMI example design

 

BTW, xapp1287 is a bit old. if you use Vivado v2016.3 and later version, you can generate the HDMI reference design by highlighting the HDMI IP -> Right Click it -> Open IP example design.

 

For more details on how to generate IP example design and associated SDK workspace, please refer to latest PG235 -> Chapter 5.

 

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Adventurer
Adventurer
4,202 Views
Registered: ‎06-13-2012

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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Hi,

 

Thank you for your answer xud, I understand the level shift to TMDS, but on inrevium board before TI SN65DP159 there's a clock multiplexer TS3USB221. The multiplexer has two clock input and a single output, I want to avoid the multiplexer and use only the Tx_Ch3_MGT_p/n (with a level shifter) in order to use the comlpete transceiver quad and save LVDS pins.

Is that possible?

 

Regards

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Xilinx Employee
Xilinx Employee
4,194 Views
Registered: ‎08-02-2007

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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I see what you mean now.  Yes, it's possible.

 

ZCU102 board actually doesn't use TS3USB221, it drives HDMI_TX_LVDS_OUT pairs directly to DP159 (level shifter). HDMI TX Subsystem IP can function well on that board. 

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Adventurer
Adventurer
4,189 Views
Registered: ‎06-13-2012

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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Hi xud,

 

I'm sorry but there's still a misunderstood, I would like to avoid use the LVDS pin output from a HR/HP bank and use only the GTH bank pins to "generate" the HDMI_TX_LVDS_OUT.

ZCU102 board uses HDMI_TX_LVDS_OUT from bank 65 that's the scenario I would like to avoid.

I want to know if I can generate HDMI_TX_LVDS_OUT with a GTH output, as an example with ZCU102 using pins MGTHTXP3_P/N.

 

The question comes from the mux present in the inrevium board that let me think it's possible to use a GTH output to generate the clock signal.

 

Thank you for your support

 

regards

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Xilinx Employee
Xilinx Employee
7,524 Views
Registered: ‎08-01-2007

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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The Video PHY Controller v2.0 does not support generating the TMDS Clock from the unused GTH in a quad.

The source for the Video PHY Controller is in clear text and you could modify it to use the Video PHY and the Driver to generate the clock with the unused GTH.  This flow is not officially supported, once you modify the code you are responsible for testing and verification.

Chris
Video Design Hub | Embedded SW Support

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Explorer
Explorer
3,621 Views
Registered: ‎04-19-2016

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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Hello, 

 

I use xapp1287 application project in my ZC706 board. I wonder this could I give the both HDMI clocks ( 148.5 MHz) from PS ( Zynq) side? 

 

  • One another thing xapp1287 is withdrawn? ( obsolote now? ). Will  be HMDI Tx and Rx Subsytstem IP also withdrawn? ( obslote)

 

Thank you,

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Xilinx Employee
Xilinx Employee
3,557 Views
Registered: ‎08-02-2007

Re: HDMI 2.0 Tx_TMDS_CLK_p/n source

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@doner_t Firstly please open a new thread on this question.

 

Since 2016.3, we provide HDMI board example design in Vivado.

 

In latest Vivado 2017.2, you can generate ZC706 HDMI example design (including SDK workspace), which uses Zynq Process (not microblaze), please refer to chapter 2 of PG236/PG235 for step-by-step instructions.

 

 

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