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Visitor pierre92
Visitor
450 Views
Registered: ‎12-07-2016

HDMI GTH pin swap

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Hi,

I'm designing an HDMI interface (receiver) using the Vid Phy IP (my FPGA is  XCZU4EV-1FBVB900E)

In order to ease CAD, I had to swap data D0 with D1. see schematic below:

hdmi_schema.PNG

To compensate this swap, I inverted the data between Vid Phy and HdmiRxSS IP. See below:

phy_mac_swap.PNG

Is it possible to do it like this?

Or is it better to do it in the top of the FPGA? If yes, how to do it?

I'm asking this because I have some issues with the HdmiRxSS. 

Thanks

Pierre.

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1 Solution

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Moderator
Moderator
406 Views
Registered: ‎11-09-2015

Re: HDMI GTH pin swap

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HI @samk ,

Acutally, the video phy expects the lanes to be aligned. It will create the constraints accordingly

phy_rxn[0] will be mapped to GT0, phy_rxn[1] will be mapped to GT1 etc...

 

@pierre92 

We have seen some customers doing the way you are doing, so it seems to work. But we did not do any hardware testing for this configuration.

Another way yould be to overwrite the constraints generated by the video phy. This is done on the ZCU102 design for Displayport 1.2 but could also be applied for HDMI. In your master tcl file, you would need to remove the location constraint of the GT before assigning the pins locations:

set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]


## DP RX pins
set_property PACKAGE_PIN H1 [get_ports {phy_rxn_in[0]}]
set_property PACKAGE_PIN H2 [get_ports {phy_rxp_in[0]}]
set_property PACKAGE_PIN J4 [get_ports {phy_rxp_in[1]}]
set_property PACKAGE_PIN J3 [get_ports {phy_rxn_in[1]}]
set_property PACKAGE_PIN F1 [get_ports {phy_rxn_in[2]}]
set_property PACKAGE_PIN F2 [get_ports {phy_rxp_in[2]}]
set_property PACKAGE_PIN K2 [get_ports {phy_rxp_in[3]}]
set_property PACKAGE_PIN K1 [get_ports {phy_rxn_in[3]}]

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

2 Replies
Moderator
Moderator
420 Views
Registered: ‎10-04-2017

Re: HDMI GTH pin swap

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Hi @pierre92 ,

 

It is best to do any pin swapping on the top level and to follow connection guidelines between the PHY and HDMI SubSystem. 

The next question is: Does the GT ordering matter? Looking at PG230, I do not see any requirements for the ordering of the GTs.  (Specifically Chapter 5 Board Design Guidelines). Based on this, I do not see any requirements for phy_rxn[0] to be assigned to HGTHRXN0.

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Moderator
Moderator
407 Views
Registered: ‎11-09-2015

Re: HDMI GTH pin swap

Jump to solution

HI @samk ,

Acutally, the video phy expects the lanes to be aligned. It will create the constraints accordingly

phy_rxn[0] will be mapped to GT0, phy_rxn[1] will be mapped to GT1 etc...

 

@pierre92 

We have seen some customers doing the way you are doing, so it seems to work. But we did not do any hardware testing for this configuration.

Another way yould be to overwrite the constraints generated by the video phy. This is done on the ZCU102 design for Displayport 1.2 but could also be applied for HDMI. In your master tcl file, you would need to remove the location constraint of the GT before assigning the pins locations:

set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC "" [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[26].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]


## DP RX pins
set_property PACKAGE_PIN H1 [get_ports {phy_rxn_in[0]}]
set_property PACKAGE_PIN H2 [get_ports {phy_rxp_in[0]}]
set_property PACKAGE_PIN J4 [get_ports {phy_rxp_in[1]}]
set_property PACKAGE_PIN J3 [get_ports {phy_rxn_in[1]}]
set_property PACKAGE_PIN F1 [get_ports {phy_rxn_in[2]}]
set_property PACKAGE_PIN F2 [get_ports {phy_rxp_in[2]}]
set_property PACKAGE_PIN K2 [get_ports {phy_rxp_in[3]}]
set_property PACKAGE_PIN K1 [get_ports {phy_rxn_in[3]}]

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post