12-10-2018 07:34 PM - edited 12-12-2018 02:10 AM
I'm working on an HDMI design based on the Xilinx linux ZCU102 pass through example design.
I'm observing minor glitches (white lines in the video) with a board and suspect the issue has to do with the HDMI RX side.
Also, In another board, HDMI RX data is not being received properly. I don't see the HDMI_hb helper core status toggling.
In working board, I do see this helper core status output (for RX path) toggling and design works fine at 4K 60fps. I have ensured that the hardware settings in both working and non working boards are kept same.
Is it possible to change/tune the vphy controller parameters and solve this problem?
01-10-2019 02:11 AM
12-10-2018 09:28 PM
12-10-2018 10:44 PM - edited 12-12-2018 02:12 AM
12-11-2018 08:10 AM
In addition to the video requested from @watari, can you also add:
12-12-2018 01:34 AM
I work offline on this issue with Vinay,
He has probed the HDMI RX cable clock (RX reference clock to VPHY ) and notices it stops and recovers for every 16sec or so. This is observed with 4K 60fps input.
He has confirmed that the RX HPD output will not toggle during the issue and remains asserted high.
In the meantime, the same clock remains stable with 4K 30fps input and the design works fine.
Is there anything in the design that could effect the reference clock to stop at certain times?
12-12-2018 01:37 AM
At which point do you measure the clock? It normally indicates the quality of clock or HDMI cable.
Video PHY has RX clock detection module, if the clock range is outside of the tolerance range, it won’t consider RX clock as a stable clock.
Also you need to check if there is some problem with retimer on your board. What do you have on board between the RX TMDS clock from RX cable and the clock driven to FPGA? Please probe both clocks, and see if there is issue with retimer.
01-10-2019 02:11 AM
01-16-2019 03:43 AM
As this issue is now solved for you, could you kindly close the topic by marking a reply as accepted solution?
Thanks and Regards,