01-24-2014 01:57 AM
I am trying to get HDMI / DVI video from th Atlys.
In this topic here,
there is a discussion how to run the two demos "vct_demo" and "dvi_demo" coming with the XAP 495. I tried to compile them (with ISE 14.6 and 14.7) and failed because of the following errors:
for the dvi_demo:
ERROR:HDLCompiler:1511 - "C:\Xil\AtlysDemos\Atlys_495_TMDS\rtl\rx\serdes_1_to_5_diff_data.v" Line 82: Mix of blocking and non-blocking assignments to variable <inc_data_int> is not a recommended coding practice.
for the vct_demo:
ERROR:PhysDesignRules:2502 - Issue with pin connections and/or configuration on
block:<sysclk_div>:<BUFIO2_BUFIO2>. BUFIO2 has an invalid setting of DIVIDE
by 2. This setting is not supported. For more information please see Answer
ERROR:Pack:1642 - Errors in physical DRC.
I simply imported all the *.v files as well as the corresponding *.ucf and pressed implement. For both of the projects, I double checked if all *.v referenced are found and this is the case. Nothing is missing. The Chip is set correctly to the Atlys' Spartan too.
Anybody there, who has an idea adout that?
I checked the answer record referenced, but it did not help,
Other examples for the Atyls I took from the web compile and do work fine, so it does not seem to be a general problem of the 14.6 or 14.7 or Spartan or the Atlys or any project setting.
Can this here be a simple version issue? - Is it a matter of error level which is stricter than in former versions?
Can somebody confirm that the example compiles with former versions? Which one?
I have seen, that in the docu 12.4 was referenced to work properly. For some reasons, I cannot use versions below 14.x easily here and should have very strong reasons to work with older ISE versions.
I already inspected these threads with similar issues but got no help.
Any help is appreciated.
01-24-2014 02:01 AM
Of course I also would be interested in a working Xilinx Project.
Since i do not expect that people are willing or are allowed to post their business work (code) here, I would also be confident with a Xilinx Atlys bit-file - just to proove to my me and my boss, that this Atlys board here and it's HW works for HDMI output and it is worth continuing.
02-14-2014 11:57 PM
I am getting the same error whilst trying to build xapp495 using ise 14.7. Another discussion suggested xapp495 was originally designed and build using ise 12.3. The dvi_demo blocking issue produced only a warning in earlier ise versions. However, it's the vtc_demo issue I'd like to resolve. Did you manage to resolve your problem eventually?
02-22-2014 12:10 AM
04-08-2014 01:44 PM
04-10-2014 05:07 PM
Hm, I do not completely understand, what is the point about thih and how I an correct this.
Does this mean, that in former Xilinx Versions this was an undisvocered / accepted bad decription which now is promoted to en error?
Or is the design not right at all?
07-30-2014 08:04 AM
In answering the above question: Issue 1 is solved the given way by uncommenting the relevat code line (#234 //inc_data_int <= debug_in ; )
but the other issue with the VTC-DEMO is still there. No idea about this. I am sure I have added all files, there is nothing marked missing in the project view.
The tool still reports the error with the BUFIO_2, but I am not even able to locate this in the files. I assume this is an automatically instantiated buffer, performed by the tool, but without impropper settings or whatever.
07-30-2014 08:18 AM
Here are the relevant lines:
In one file, they use 25MHz, in the other one 50MHz
// 25 MHz and switch debouncers
wire clk25, clk25m;
BUFIO2 #(.DIVIDE_BYPASS("FALSE"), .DIVIDE(5))
sysclk_div (.DIVCLK(clk25m), .IOCLK(), .SERDESSTROBE(), .I(clk100));
BUFG clk25_buf (.I(clk25m), .O(clk25));
DOES NOT WORK
IBUF sysclk_buf (.I(SYS_CLK), .O(sysclk));
BUFIO2 #(.DIVIDE_BYPASS("FALSE"), .DIVIDE(2))
sysclk_div (.DIVCLK(clk50m), .IOCLK(), .SERDESSTROBE(), .I(sysclk));
BUFG clk50m_bufgbufg (.I(clk50m), .O(clk50m_bufg));
Devide by 2 makes sense to me, because of the 100MHz OSC used with ATLYS.
12-08-2014 03:58 PM
I am currently struggling with this same issue. Starting with ISE 14.6, the use of the divide by 2 setting in BUFIO2 was promoted from warning to fatal error. See this page, aka Answer Record 56113:
That page details some potential solutions, which are all methods of generating the required 50 MHz signal from the 100 MHz system clock.
12-08-2014 06:52 PM
For the record, I was able to get the vtc_demo to work in ISE 14.6 by modifying vtc_demo.v thusly:
// Original code, doesn't work on ISE >= 14.6 // BUFIO2 #(.DIVIDE_BYPASS("FALSE"), .DIVIDE(2)) // sysclk_div (.DIVCLK(clk50m), .IOCLK(), .SERDESSTROBE(), .I(sysclk)); wire clkfb; DCM_SP #( .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1), .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("TRUE"), .CLKIN_PERIOD(10.0), .CLKOUT_PHASE_SHIFT("NONE"), .CLK_FEEDBACK("1X"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), .DLL_FREQUENCY_MODE("LOW"), .DSS_MODE("NONE"), .DUTY_CYCLE_CORRECTION("TRUE"), .FACTORY_JF(16'hc080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) DCM_SP_inst ( .CLK0(clk50m), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLK90(), .CLKDV(), .CLKFX(), .CLKFX180(), .LOCKED(), .PSDONE(), .STATUS(), .CLKFB(clkfb), .CLKIN(sysclk), .DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .RST(1'b0) ); BUFIO2FB #( .DIVIDE_BYPASS("TRUE") ) BUFIO2FB_inst ( .O(clkfb), .I(clk50m) );