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Observer yuko.2828
Observer
1,087 Views
Registered: ‎12-27-2018

HDMI TX/RX PLL selection

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Hi all,

I want to implement HDMI TX/RX Pass-throuh example design targeting MPSoC US+. (Planning to use device with single GTH quad)

1. Xilinx Video PHY controller document mentioned that if I choose QPLL for HDMI TX I have to CPLL for HDMI RX.

    Why ? Can I use CPLL for both HDMI TX and HDMI RX  ? 

2. Can I use the same REFCLK for HDMI TX & RX ? ( I believe so)

 

Thanks

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Xilinx Employee
Xilinx Employee
1,010 Views
Registered: ‎08-02-2007

Re: HDMI TX/RX PLL selection

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@yuko.2828

1. What you are trying to do is called "bonded mode". It is only supported in 7 Series GTX family. It can only be done in the software by setting both TXSYSCLKSEL (and TXPLLCLKSEL) and RXSYSCLKSEL (and RXPLLCLKSEL) bits of RCS register to CPLL or QPLL. Setting the same  

PLL selection for TX and RX in Video PHY GUI causes a parameter validation error"

2. If you want to use the same REFCLK, you don't have to set it on GUI. It depends on your application :

- Firstly you need to ensure the required refclk frequency are the same between HDMI TX and RX. For example, both 4kp60 and 1080p60 RGB requires 148.5Mhz refclk.

- The reference clock frequency is in supported range of QPLL or CPLL. For QPLL1 GTHE4 in Vivado v2018.3, the min supported frequency is 50Mhz. You need to ensure required REFCLK frequency > 50MHz. For example, 720x480p60 needs 27MHz refclk, which can't be implemented with the same reference clock, as RX side needs to use DRU clock, and TX side will apply oversampling, the TX and RX refclk frequency won't be the same.

- If HDMI TX and RX are in the different quad, you need to make sure the REFCLK selection (refclk, northrefclk, southrefclk) should follow the GT requirement. You need to refer to UG576 for more details on that

6 Replies
Xilinx Employee
Xilinx Employee
1,058 Views
Registered: ‎03-07-2018

Re: HDMI TX/RX PLL selection

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Hello @yuko.2828

1. Xilinx Video PHY controller document mentioned that if I choose QPLL for HDMI TX I have to CPLL for HDMI RX.

    Why ? Can I use CPLL for both HDMI TX and HDMI RX  ? 

>>>> As per PG230 (Page 65) , The Video PHY Controller core allows you to choose whether the QPLL0/1 or the CPLL is used by the transmitter. The receiver should use the other PLL that is not used by TX.

For more details please check  PG230 (Page 65, 67, 69)

2. Can I use the same REFCLK for HDMI TX & RX ? ( I believe so)

>>>> I believe MGTREFCLK0/MGTREFCLK1 can be used when Advanced Clock Mode is disabled or when GTREFCLK0/GTREFCLK1 is selected as one of the input clock sources in HDMI. For more information check PG230 (Page 12). User can select same MGTREF clock in GUI of video phy controller IP. But I have not tested this on board, so I need check this possibility internally. 

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
1,011 Views
Registered: ‎08-02-2007

Re: HDMI TX/RX PLL selection

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@yuko.2828

1. What you are trying to do is called "bonded mode". It is only supported in 7 Series GTX family. It can only be done in the software by setting both TXSYSCLKSEL (and TXPLLCLKSEL) and RXSYSCLKSEL (and RXPLLCLKSEL) bits of RCS register to CPLL or QPLL. Setting the same  

PLL selection for TX and RX in Video PHY GUI causes a parameter validation error"

2. If you want to use the same REFCLK, you don't have to set it on GUI. It depends on your application :

- Firstly you need to ensure the required refclk frequency are the same between HDMI TX and RX. For example, both 4kp60 and 1080p60 RGB requires 148.5Mhz refclk.

- The reference clock frequency is in supported range of QPLL or CPLL. For QPLL1 GTHE4 in Vivado v2018.3, the min supported frequency is 50Mhz. You need to ensure required REFCLK frequency > 50MHz. For example, 720x480p60 needs 27MHz refclk, which can't be implemented with the same reference clock, as RX side needs to use DRU clock, and TX side will apply oversampling, the TX and RX refclk frequency won't be the same.

- If HDMI TX and RX are in the different quad, you need to make sure the REFCLK selection (refclk, northrefclk, southrefclk) should follow the GT requirement. You need to refer to UG576 for more details on that

Observer yuko.2828
Observer
1,000 Views
Registered: ‎12-27-2018

Re: HDMI TX/RX PLL selection

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Hi Bhushan

Thanks for your answer !!

 

Hi Xud

You clarified a lot ! Thank you.

Spent time to read HDMI and Video PHY document today. 

Unfortunately, my device has only a single GTH quad and 3 REFCLK is needed since I need to use NI-DRU too to support low resolution format. I don’t think I have a solution for my problem. I need to use device with different package with multiple GTH quads.

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Observer yuko.2828
Observer
999 Views
Registered: ‎12-27-2018

Re: HDMI TX/RX PLL selection

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@xud, @bpatil

Do you have any document/table to calculate the REFCLK requirement for a specific video format ?
Do I have to read the driver source code ? 

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Xilinx Employee
Xilinx Employee
995 Views
Registered: ‎08-02-2007

Re: HDMI TX/RX PLL selection

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@yuko.2828

Please take a look at the clocking section of PG235/PG236, Table 32 explains the relationship between different clocks, and an example (1080p60, 12BPC, and 2PPC) are used to show how clock frequency is calculated based on exact resolution. Please also take a look at CEA-861 spec, it has a table providing pixel clock frequency for associated resolution (with VIC code)

Video PHY RX and TX can be placed in the same quad, you don't have to implement them to two quads. The main problem is you need to have a GT REFCLK IO running at 156MHz for DRU clock.

Observer yuko.2828
Observer
982 Views
Registered: ‎12-27-2018

Re: HDMI TX/RX PLL selection

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Xud, Thank you !!
Understood !

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