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HDMI TX SS example

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Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016
Accepted Solution

HDMI TX SS example

Hello, 

 

In TX only example from Vivado for HDMI TX SS module is not supporting 4k resolution. When I select the 4K resolution in serial communication, I get the response negative as it can be seen below where I select 8 and 7.

 

---------------------------
---   RESOLUTION MENU   ---
---------------------------
 1 -  720 x 480p
 2 -  720 x 576p
 3 - 1280 x 720p
 4 - 1680 x 720p
 5 - 1920 x 1080p
 6 - 2560 x 1080p
 7 - 3840 x 2160p
 8 - 4096 x 2160p
 9 - 1920 x 1080i
10 -  640 x 480p (VGA / DMT0659)
11 -  800 x 600p (SVGA / DMT0860)
12 - 1024 x 768p (XGA / DMT1060)
13 - 1280 x 768p (WXGA / CVT1260E)
14 - 1366 x 768p (WXGA+ / DMT1360)
15 - 1280 x 1024p (SXGA / DMT1260G)
16 - 1680 x 1050p (WSXGA+ / CVT1660D)
17 - 1600 x 1200p (UXGA / DMT1660)
18 - 1920 x 1200p (WUXGA / CVT1960D)
19 - 1152 x 864p (Custom)
99 - Exit
Starting colorbar> 8
Unable to set requested TX video resolution.
Returning to previously TX video resolution.
VPHY Error: See log for details
Starting colorbar> 7
Unable to set requested TX video resolution.
Returning to previously TX video resolution.
VPHY Error: See log for details
Starting colorbar> 9
TX stream is down
TX stream is up
--------
Colorbar :
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Interlaced
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz (I)
        Pixel Clock:      74250000
--------

May I know why is that? and how to overcome this problem to support 4K resolution? Where can I check log?

 

Thanking you 

Best regards


Accepted Solutions
Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

@tim_severance@xud

 

I don't know why it behaved such.

 

I just put these lines in the place where it is shown in the code 

xil_printf("IsStreamUp %d\n",IsStreamUp);
xil_printf("SinkReady %d\n",SinkReady);

		if (IsStreamUp && SinkReady) {
			xil_printf("IsStreamUp %d\n",IsStreamUp);
			xil_printf("SinkReady %d\n",SinkReady);
			IsStreamUp = FALSE;
			i2c_dp159(&Vphy, 0, TxLineRate);
			XVphy_Clkout1OBufTdsEnable(&Vphy, XVPHY_DIR_TX, (TRUE));
		}

Then I put below line in enablecolorbar function, just before the I2CCLK call.

xil_printf("VphyPtr->HdmiTxRefClkHz %d \n", VphyPtr->HdmiTxRefClkHz);

 

Now 4k works. I don't know why !!!! the print statement shouldn't make any difference. 

 

Info on 4K now:

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 1
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 148500480 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 2

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 5 - Clk1Div : 10 - Clk2Div : 5

DRU Settings
-------------
Version  : 7
DRU is disabled

2K info 

 

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 1
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 148500480 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 2

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 5 - Clk1Div : 10 - Clk2Div : 5

DRU Settings
-------------
Version  : 7
DRU is disabled

If anyone knows the explanation, then please let me know.

 

Thank you 

Best regards 

View solution in original post


All Replies
Moderator
Posts: 3,643
Registered: ‎11-09-2015

Re: HDMI TX SS example

Hi @msh,

 

Basic question: Do you have any 4K monitor connected? The design won't sent 4K if the monitor cannot receive it. So it might be that your monitor only supports 1080p

Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

hi @florentw

 

I have Samsung U28E5908 model which supports 4K UHD (3840X2160)

 

https://www.1000ordi.ch/samsung-u28e590d-lu28e590ds_en-93334_fr.pdf

 

 

Best regards 

Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

hi @florentw

 

I also read the same problem here 

https://forums.xilinx.com/t5/Video/v-hdmi-tx-ss-0-ex-Unable-to-set-requested-TX-video-resolution/td-p/844153

 

It is solved via HDMI 2.0 DDC readback after 1920x1080x60p, but I do not know how to do so? 

 

also in the example project the encryption is disabled.

 

Thanks 

Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

Hi, 

 

here is the log that I able to find, where I can see that QPLL configuration is not found. How to solve this problem?

 


VPHY log
------
GT init start
GT init done
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
Error! QPLL config not found!
VPHY Error: See log for details

Xilinx Employee
Xilinx Employee
Posts: 251
Registered: ‎08-02-2007

Re: HDMI TX SS example

@msh

 

Do you see this problem on Xilinx board or your own board?

 

Normally Samsung TV has more than one HDMI socket, have you tried all of them. 

 

How do you drive the TX refclk? Normally this error occurs when the userclk frequency isn't correct or the clock jitter is too much.

 

Can you dump the Video PHY register? 

Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

 

@xud

 

Xilinx board : ZCU106

 

Yes I tried all the HDMI socket and tried sony monitor also (which supports 4K)

 

This is an example from Xilinx (which appears when we do right click and IP example). Though I see application clock from PS to be 300 Mhz. But maybe it is reconfigured via PS as the serial log states pixel clock 594 Mhz.

 

 

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version is not available for reading as HDMI TX Video Clock is not ready.

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 0
Sample rate: 0

Audio
---------
Format   : L-PCM
Channels : 0
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 0 Hz
TX: QPLL0
RX: CPLL
TX state: idle
RX state: idle

QPLL0 settings
-------------
M : 0 - N : 0 - D : 0

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

DRU Settings
-------------
Version  : 7
DRU is disabled

 

Also, when I run below code, I get into else statement. Which I think is not correct as the monitor supports 4K.

 

XV_HdmiTxSs_DetectHdmi20(&HdmiTxSs);
if (HdmiTxSs.HdmiTxPtr->Stream.IsHdmi20)
 xil_printf("HdmiTxSs->HdmiTxPtr->Stream->IsHdmi20 = 1.\r\n");
else
 xil_printf("\x1b[31mHdmiTxSs->HdmiTxPtr->Stream->IsHdmi20 = 0.\r\n\x1b[0m");
break;

There is no register dump. Maybe because I am using trial version license.

 

 Capture.PNG

 

Please let me know how can I resolve this problem?

 

Thanks 

 

Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

@xud @florentw

 

I would like to give additional information. I see these warning in serial out when I check EDID:

 

Warning: Connected Sink's EDID indicates HDMI 2.0 capable, but the SCDC read request register bit 
(VSDB:RR_Capable) is not asserted
Warning: Connected Sink's EDID indicates HDMI 2.0 capable, SCDC present and capable of initiating 
read request, however the SCDC is inaccessible
Warning: Connected Sink's EDID indicates Deep Color of 10 BpC Not Supported
Warning: Connected Sink's EDID indicates Deep Color of 12 BpC Not Supported
Warning: Connected Sink's EDID indicates Deep Color of 16 BpC Not Supported

Here is the proof that HDMI 2 support 4K with 60 Hz in Samsung monitor

Capture_new.PNG

 

Explorer
Explorer
Posts: 195
Registered: ‎10-31-2016

Re: HDMI TX SS example

Info reply on 4K HDMI2 

 

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 198004736 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16

DRU Settings
-------------
Version  : 7
DRU is disabled

info reply on 2K HDMI2

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       2560x1080@60Hz
        Pixel Clock:      198000000

        HSYNC Timing: hav=2560, hfp=248, hsw=44(hsp=1), hbp=148, htot=3000 
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=011, vtot=1100
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 198002688 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16

DRU Settings
-------------
Version  : 7
DRU is disabled
 

Please let me know if this gives any clue.

 

Thank you 

Best regards 

Xilinx Employee
Xilinx Employee
Posts: 251
Registered: ‎08-02-2007

Re: HDMI TX SS example

@msh

 

The clock isn't configured properly. For 4Kp60 RGB, the TX reference clock should be running at 148.5 MHz(594MHz/4)

 

Your TX reference clock frequency: is running at 200Mhz.

 

How do you driver TX reference clock ? Have you configure it to 148.5 MHz?

 

You can firstly switch TX to DVI mode, so you don't need to worry about SCDC read request register bit  warning.

 

The issue is still related to Video PHY. it's very important to print out the register dump. Following is an example to dump VPHY register dump in xsct command line :

"mrd 0x44A40000 200"

 

0x44A40000 should be changed to the base address of Video PHY in your design. You can find it in Address Editor Tab when you open IPI.

I don't see any reason why you can't dump it.