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Visitor nleclerc
Visitor
462 Views
Registered: ‎03-07-2016

HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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Hi,

  I am struggling with the HDMI TX subsystem v3.1.  We have a somewhat working design on another platform that uses version 3.0 (2017.3) and we are moving toward 2018.2 using version 3.1.

  It would seem like the link between the HDMI core and the Video Phy core has changed from 40 bits down to 20 when using 2 pixels per clock.  I just wanted to confirm that this is right since documentation doesn't show this at all; it still shows 40 bits of data width on this interface for the two mode of transport (2PPC or 4PPC).  This implies that the link clock must be twice as fast as before.

  Has anyone used version 3.1 of the subsystem yet?

 

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Visitor nleclerc
Visitor
260 Views
Registered: ‎03-07-2016

Re: HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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Hi,

  There is no solution, the fact is that it did change.  I managed to get it working.  No answers helped on this issue.

Thanks anyway, any insight is appreciated.

 

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4 Replies
Scholar beandigital
Scholar
417 Views
Registered: ‎04-27-2010

Re: HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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The link data width is a multiple of 10-bits. So for 2PPC it will be 20-bits.
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Scholar watari
Scholar
400 Views
Registered: ‎06-16-2013

Re: HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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Hi @nleclerc

 

Would you make sure video format ?

 

As you mentioned before, it seems that video format is YCbCb 10bit mode. (Like ITU-BT.656 and BT.1120)

Is it correct ?

 

I guess you set YCrCb 16bit as ITU BT.1120. So your bus width is 32bit.

 

Would you explain more details ?

 

Also, would you tell me target resolution and frame rate, too ?

 

Best regards,

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Moderator
Moderator
328 Views
Registered: ‎11-09-2015

Re: HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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Hi @nleclerc,

Do you have any update on this? Were the replies from @watari or @beandigital enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor nleclerc
Visitor
261 Views
Registered: ‎03-07-2016

Re: HDMI TX Subsystem - Link data width for 2 samples per clock changed from version 3.0 to version 3.1

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Hi,

  There is no solution, the fact is that it did change.  I managed to get it working.  No answers helped on this issue.

Thanks anyway, any insight is appreciated.

 

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