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Explorer
Explorer
516 Views
Registered: ‎08-31-2016

HDMI VPHY Controller : [Constraints 18-1056] Critical warning related to clock constraints

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Hi, I'm facing this critical warning lately. The clock constraints here are conflicting as indicated in the below message. As far as I know, both the constraints are generated automatically during OOC runs. I haven't constrained this 'mgtrefclk0_pad_p_in_0' clock in my top XDC file. Will constraining 'mgtrefclk0_pad_p_in_0' in top XDC file do any favor to resolve this critical warning? 

Please let me know a resolution for this.

[Constraints 18-1056] Clock 'hdmi_example_zcu102_vid_phy_controller_0_0_mgtrefclk0_pad_p_in' completely overrides clock 'mgtrefclk0_pad_p_in_0'.
New: create_clock -period 3.367 -name hdmi_example_zcu102_vid_phy_controller_0_0_mgtrefclk0_pad_p_in [get_ports mgtrefclk0_pad_p_in_0], ["d:/example_design/design.srcs/sources_1/bd/hdmi_example_zcu102/ip/hdmi_example_zcu102_vid_phy_controller_0_0/vid_phy_controller_xdc.xdc": and 61]
Previous: create_clock -period 10.000 -name mgtrefclk0_pad_p_in_0 [get_ports mgtrefclk0_pad_p_in_0], ["D:/example_design/design.srcs/sources_1/bd/hdmi_example_zcu102/hdmi_example_zcu102_ooc.xdc": and 9]

Regards,

Vinay Shenoy

Vinay Shenoy
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Moderator
Moderator
486 Views
Registered: ‎11-09-2015

Re: HDMI VPHY Controller : [Constraints 18-1056] Critical warning related to clock constraints

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Hi @vinay_shenoy,

I am quite sure you can ignore this warning. This might be because the GT wrapper under the video phy generates a constraints and then the video phy (upper layer) overwrites it.

I do not think writing a new constraints will avoid this.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Moderator
Moderator
487 Views
Registered: ‎11-09-2015

Re: HDMI VPHY Controller : [Constraints 18-1056] Critical warning related to clock constraints

Jump to solution

Hi @vinay_shenoy,

I am quite sure you can ignore this warning. This might be because the GT wrapper under the video phy generates a constraints and then the video phy (upper layer) overwrites it.

I do not think writing a new constraints will avoid this.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
451 Views
Registered: ‎11-09-2015

Re: HDMI VPHY Controller : [Constraints 18-1056] Critical warning related to clock constraints

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HI @vinay_shenoy,

Do you have any updates on this? Was to answer provided enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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