UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
234 Views
Registered: ‎05-05-2018

HDMI YUV420 4Kp60 Support

Jump to solution

I am trying to get the HDMI Tx example design to output 4Kp60 video with 4:2:0 8-bit video (ie: 297 MHz pixel rate) vs. the full HDMI 2.0 594 MHz. rate, so far without success.

I created the example FPGA design from what I believe is an appropriately configured HDMI_Tx_Ss IP block (checked both NTSC/PAL and YUV420 support, 8 bit/component max, 2 pixels/clock) and the corresponding software example running on the R5.

My target platform is the ZCU704 with Vivado 2018.1.  I have no problems switching video patterns, colorspace, or resolution as long as I stay with 1080p or below.  When I attempt to run 4Kp60 with 4:2:0 I think the clocking is incorrect, as "info" reports the pixel clock is 594 MHz when I would expect to see 297.  The Rx device is based on an Analog Devices ADV7619 which can run up to 297 MHz pixel rates and supports 4Kp60 with YUV 4:2:0.

Any advice on how to enable 4Kp60 4:2:0 8-bit video?

The only thing that seems odd is when I try to select the 4K resolution, the console prints the following error:

VPHY Error: See log for details

...and the log contains:

Error! QPLL config not found!

 

The "info" command reports the following when I have the system in 4K mode:

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX
    : VTC Core
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI
HDMI Video Mask is Disabled

        Color Format:     YUV_420
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
Video Frame CRC
------------

CRC PPC     =  2
CRC - R/Y   =  0xAB5B
CRC - G/Cr  =  0xAB5B
CRC - B/Cb  =  0xD777

------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 297162752 Hz
TX: QPLL0
TX state: ready

QPLL0 settings
-------------
M : 1 - N : 40 - D : 4

TX MMCM settings
-------------
Mult : 4 - Div : 1 - Clk0Div : 8 - Clk1Div : 4 - Clk2Div : 8


Any help would be greatly appreciated!

0 Kudos
1 Solution

Accepted Solutions
78 Views
Registered: ‎05-05-2018

Re: HDMI YUV420 4Kp60 Support

Jump to solution

UPDATE:

Playing with the monitor settings screen I was able to get the monitor to advertise 4:2:0 modes on one of the HDMI ports.  This did not seem to affect the HDMI Example design behavior.

However, after modifications to suit my application (FPGA: remove the Xilinx pattern generator logic, switch the video interface to native pixel mode / SW: enable 4:2:0 mode and remove instances of the HDMI Example app that talk to the now missing pattern generator) I was able to get the HDMI Tx logic to properly run in the three modes I need supported (4K60p/297 MHz/4:2:0, 1080p60/148.5 MHz/4:2:2, 720p/74.25 MHz/4:2:2).

0 Kudos
7 Replies
Highlighted
216 Views
Registered: ‎05-05-2018

Re: HDMI YUV420 4Kp60 Support

Jump to solution

UPDATE:

I acquired a full HDMI 2.0 4K monitor and have managed to get various 4K output modes to work, but YUV_420 is still broken.

At launch, the demo application outputs colorbars at 1080p60.  If I change the resolution to 4K (3840 x 2160p, option 7) the new HDMI 2.0 monitor properly displays the updated colorbars at 4Kp60.  I can then go to the Color space menu and change between RGB, YUV444, and YUV422 without issue.  However, as soon as I select YUV420, the display complalins that no signal is detected and the only way I have figured out to recover is to reboot (ie: reprogram the FPGA).  I can halt and restart the R5 core running the HDMI demo and it will *NOT* restore the output signal.

Any advice would be appreciated!

0 Kudos
Scholar watari
Scholar
190 Views
Registered: ‎06-16-2013

Re: HDMI YUV420 4Kp60 Support

Jump to solution

Hi @cdsteinkuehler 

 

What monitor do you use ?

 

Best regards,

0 Kudos
182 Views
Registered: ‎05-05-2018

Re: HDMI YUV420 4Kp60 Support

Jump to solution

I am using a Vizio V405-G9 which supports full HDMI 2.0 and a custom ADV7619 based Rx device which supports 4Kp60 at 4:2:0.

With either option, once I switch the ZCU104 to YUV420 colorspace, it effectively disables the HDMI output and I am unable to restore a working output without reprogramming the FPGA.  I can select other resolutions, bit depths, and color spaces, and even stop and re-launch the HDMI Tx example application (running on a Cortex-R5 core), but after selecting YUV420 I never get a valid HDMI output again until I reprogram the FPGA (via power cycle or a warm reboot).

0 Kudos
Scholar watari
Scholar
178 Views
Registered: ‎06-16-2013

Re: HDMI YUV420 4Kp60 Support

Jump to solution

Hi @cdsteinkuehler 

 

I just ask you "does this monitor support YUV420 as external input via HDMI ?"

I can't find whether this monitor support it or not.

 

Best regards,

0 Kudos
168 Views
Registered: ‎05-05-2018

Re: HDMI YUV420 4Kp60 Support

Jump to solution

I'm not particularly concerned about the Vizio monitor displaying or not displaying video at 4:2:0, since it's EDID does not indicate support for VICs 96 and 97 which is what I need to generate.  I know my ADV7619 design *DOES* support those modes and it is also not working.

The main concern is why when I select YUV420 mode it seems to *PERMANENTLY* disable the example design HDMI Tx logic until the FPGA gets reprogrammed.  I would expect to be able to select YUV422 mode which displays properly on the Vizio, switch to YUV420 (which may or may not display), then switch back to YUV422 and have a working display.  It appears something fundamentally breaks with the example design any time I select the YUV420 mode, and it won't recover without reprogramming the FPGA.

0 Kudos
Xilinx Employee
Xilinx Employee
96 Views
Registered: ‎08-02-2007

Re: HDMI YUV420 4Kp60 Support

Jump to solution

@cdsteinkuehler 

From your GT status, the reference clock frequency (297Mhz) is correct :

GT status
---------
TX reference clock frequency: 297162752 Hz
TX: QPLL0
TX state: ready

Have you measured the tx_tmds clock frequency?

 

0 Kudos
79 Views
Registered: ‎05-05-2018

Re: HDMI YUV420 4Kp60 Support

Jump to solution

UPDATE:

Playing with the monitor settings screen I was able to get the monitor to advertise 4:2:0 modes on one of the HDMI ports.  This did not seem to affect the HDMI Example design behavior.

However, after modifications to suit my application (FPGA: remove the Xilinx pattern generator logic, switch the video interface to native pixel mode / SW: enable 4:2:0 mode and remove instances of the HDMI Example app that talk to the now missing pattern generator) I was able to get the HDMI Tx logic to properly run in the three modes I need supported (4K60p/297 MHz/4:2:0, 1080p60/148.5 MHz/4:2:2, 720p/74.25 MHz/4:2:2).

0 Kudos