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Visitor
Visitor
5,610 Views
Registered: ‎08-01-2016

HDMI design on virtex7 FPGA

Hi,

 

I am using virtex7 FPGA (XC7v2000T-1) and using vivado2016.2 version.

we designed a PCB board, that has HDMI Rx and Tx connectors, which connect to MGT IO's on Virtex7 motherboard. Now i generated a HDMI core from wizard and got source files including core top file (name.v).

What are the further steps i need to proceed to test pass through video on hardware.

1. Do i need to write a wrapper above core top file?. If yes, what are the mandatory signals should i bring into wrapper?

2. Do i need to modify XDC file to match with wrapper?.

 

Please give me some clear direction to proceed further.

 

Thanks,

Damoder

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Xilinx Employee
Xilinx Employee
5,606 Views
Registered: ‎08-01-2008

Re: HDMI design on virtex7 FPGA

1. Do i need to write a wrapper above core top file?. If yes, what are the mandatory signals should i bring into wrapper?
[] Yes

2. Do i need to modify XDC file to match with wrapper?.
[] Yes

 

check this example design as well

http://www.xilinx.com/support/documentation/application_notes/xapp1287-hdmi-on-fpga-gtx-transceivers.pdf

Thanks and Regards
Balkrishan
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Visitor
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Registered: ‎08-01-2016

Re: HDMI design on virtex7 FPGA

Hi Balkrishan,

 

Thanks for the quick reply.

Can you please share the source files for that example design (Including wrapper files and edited xdc files)?. It will be more helpful for me to write a wrapper to match with my design.

 

Thanks,

Damoder

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Xilinx Employee
Xilinx Employee
5,585 Views
Registered: ‎08-01-2008

Re: HDMI design on virtex7 FPGA

XAPP1287 - HDMI 2.0 Implementation on Kintex-7 FPGA GTX Transceivers Application Note ( ver1.2, 962 KB ) [PDF] ( Updated )

This application note covers the design considerations of a HDMI Interface 2.0 implementation on the Kintex-7 FPGA GTX transceiver using the performance features of HDMI with HDCP 1.4/2.2 Transmitter and Reciever Subsystems with Video PHY Controller
Design File(s)
Thanks and Regards
Balkrishan
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Visitor
Visitor
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Registered: ‎08-01-2016

Re: HDMI design on virtex7 FPGA

Hi Balakrishan,

 

I didn't find any RTL files in that design zip file.The project folder is empty in that package. Can you please share all RTL files?

Also I have one question,

Can i use different banks for MGT IO's for differential Rx and Tx pins of HDMI (I used bank 114 for Rx and bank 112 for Tx pins)?.

 

Thanks,

Damoder

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Scholar
Scholar
5,478 Views
Registered: ‎11-09-2013

Re: HDMI design on virtex7 FPGA

you need to create the project by starting tcl script.

the project will then be created for you.

 

this is explained in the file named

 

 

README.TXT

 

read it.

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Visitor
Visitor
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Registered: ‎08-01-2016

Re: HDMI design on virtex7 FPGA

Thanks. I will check that.

Can you please answer to my below question,

Can i use different banks for MGT IO's for differential Rx and Tx pins of HDMI (I used bank 114 for Rx and bank 112 for Tx pins)?.

 

Regards,
Damoder

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Scholar
Scholar
5,447 Views
Registered: ‎11-09-2013

Re: HDMI design on virtex7 FPGA

make a test design and try it out and you will know. that the best test. i assume you can as you can configure the IP core to have only TX or RX, if diff banks you need 2 times the IP Core

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