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Participant randriantsoa
Participant
333 Views
Registered: ‎06-13-2019

HDMI frame buffer

HI,

I tried to move the zcu102_hdmi_8b_exdes_2018_3 to zcu104 board with the appropriate xdc file (pinning modified for matching with zcu104 board) but I got the following error:

[DRC RTSTAT-1] Unrouted nets: 2 net(s) are unrouted. The problem bus(es) and/or net(s) are hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk0_in[0], and hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk1_in[0].

Please find enclosed the schematic.

I use Vivado 2018.3.

 

Could you help me to solve this problem?

 

Best regards,

Tags (2)
schematic.png
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7 Replies
Participant randriantsoa
Participant
297 Views
Registered: ‎06-13-2019

Re: HDMI frame buffer

Hi,

The problem could be from the xdc file. The UG1267 ZCU Evaluation board User Guide doesn't match with xdc file. For exemple, in UG 1267 page 60, HDMI_TX_LVDS_OUT_P is routed to FPGA pin H9 whereas in the zcu104.xdc file, it is routed to pin G21.

I will modify my design.

 

Best regards,

 

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Participant randriantsoa
Participant
269 Views
Registered: ‎06-13-2019

Re: HDMI frame buffer

Hi,

I tried to move zcu102 to zcu104 board with the right zcu104.sdc but I still got the same error message.

Idem for the migration of zcu106 to zcu104, I also got the same error.

[DRC RTSTAT-1] Unrouted nets: 2 net(s) are unrouted. The problem bus(es) and/or net(s) are hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk0_in[0], and hdmi_example_zcu102_i/vid_phy_controller/inst/gt_usrclk_source_inst/gtrefclk1_in[0].

Someone would have an advice?

Best regards,

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Moderator
Moderator
265 Views
Registered: ‎11-09-2015

Re: HDMI frame buffer

Hi @randriantsoa 

The pin names might not match between the ZCU104 and ZCU104 thus I am not surprised it is not working for you.

You need to understand the how to connect the GT clocking if you want to have a correct placement. I recommend you read UG576.

You need to use the correct input for the GTREFCLK. GTREFCLK0/1 if the data lanes are on the same bank or GTNORTHREFCLK/GTSOUTHREFCLK if the clock is coming from adjacent banks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
225 Views
Registered: ‎11-21-2018

Re: HDMI frame buffer

Hi @randriantsoa 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Participant randriantsoa
Participant
211 Views
Registered: ‎06-13-2019

Re: HDMI frame buffer

Hi,

Finally, I started from a Vivado IP example. I followed PG236 HDMI 1.4/2.0 Receiver Subsystem v3.1 in wich I instanciated the HDMI passthrough example, applied on ZCU104 board.

I tested it on ZCU104 board and it worked.

By the following, I added in vivado write and read frame buffers and I edited the mapping address of my design according to the mapping of the zcu102_hdmi_8b_exdes_2019_1 design.

I synthetized the design, generated the bitstream and exported the design.

For petalinux, I started from /zcu102_hdmi_8b_exdes_2019_1/apu/petalinux_bsp project.

Firstly, I copied the hdf file generated in zcu104 project above into /zcu102_hdmi_8b_exdes_2019_1/apu/petalinux_bsp/project-spec/hw-description and renamed it in system.hdf.

I modified the  following files :

- /zcu102_hdmi_8b_exdes_2019_1/petalinux_bsp /project-spec/configs/config based on zcu104-rv-ss-2018-3/petalinux/bsp/project-spec/configs/config

- /zcu102_hdmi_8b_exdes_2019_1/petalinux_bsp /project-spec/meta-user/recipes-bsp/device-trree/device-trree.bbappend as follows:

FILESEXTRAPATHS_prepend := "${THISDIR}/files:"

SRC_URI += "file://system-user.dtsi"
SRC_URI += "file://hdmi/drm-hdmi.dtsi"
SRC_URI += "file://hdmi/pl.dtsi"
SRC_URI += "file://hdmi/vcap-hdmi.dtsi"
SRC_URI += "file://zcu104/pcw.dtsi"
SRC_URI += "file://zcu104/system-conf.dtsi"
SRC_URI += "file://zcu104/zcu104-revc.dtsi"

For the files /zcu104/pcw.dtsi, /zcu104/system-conf.dtsi and /zcu104/zcu104-revc.dtsi, I used their equivalents from zcu104-rv-ss-2018-3 project.

I launched petalinux-build from /zcu102_hdmi_8b_exdes_2019_1/apu/petalinux_bsp project and generated the BOOT.BIN and image.usb files to SD card.

When I started the board, I got the error shown in the attached file.

Could you help me?

 

Best regards,

Terminal.png
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Participant randriantsoa
Participant
201 Views
Registered: ‎06-13-2019

Re: HDMI frame buffer

Hi,

 I saw the problem. The error was from the qspi flash0 partition in the system-conf.dtsi. The partition number should be 3 but not 4.

Nevertheless, I still have no HDMI passthrough. I continue my debugging.

 

Best regards,

 

Moderator
Moderator
109 Views
Registered: ‎11-21-2018

Re: HDMI frame buffer

Hi @randriantsoa 

Were you able to find the solution to your issue? 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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